Silicon-controlled rectifier structures on silicon-on insulator with shallow trench isolation
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorTa Lee Yu
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Abstract
A method to form a SCR device in the manufacture of an integrated circuit device is achieved. The method comprises providing a SOI substrate comprising a silicon layer overlying a buried oxide layer. The silicon layer further comprises a first well of a first type and a second well of a second type. A first heavily doped region of the first type is formed in the second well to form an anode terminal. A second heavily doped region of the second type is formed in the first well to form a cathode terminal and to complete the SCR device. A gate isolation method is described. A salicide method is described. LVT-SCR methods, including a floating-well, LVT-SCR method, are described.
Claims24
A method to form a SCR device in the manufacture of an integrated circuit device comprising:
- providing a SOI substrate comprising a silicon layer overlying a buried oxide layer wherein said silicon layer further comprises a first well of a first type and a second well of a second type;
- forming a first heavily doped region of said first type in said second well to form an anode terminal;
- and
- forming a second heavily doped region of said second type in said first well to form a cathode terminal;
- forming a third heavily doped region of said first type in said first well and coupling said third heavily doped region to said cathode terminal wherein no other heavily doped region lies between said second and third heavily doped regions;
- and
- forming a gate overlying said silicon layer and between said second and third heavily doped regions wherein said gate comprises a conductive layer overlying said silicon layer with an insulating layer therebetween to complete said SCR device.
A method to form a LVT-SCR device in the manufacture of an integrated circuit device comprising:
- providing a SOI substrate comprising a silicon layer overlying a buried oxide layer wherein said silicon layer further comprises a first well of a first type and a second well of a second type;
- forming a first heavily doped region of said first type in said second well to form an anode terminal;
- forming a second heavily doped region of said second type in said first well;
- forming a third heavily doped region of said first type in said first well wherein said second and third heavily doped regions are spaced apart and wherein no other heavily doped region lies between said second and third heavily doped regions;
- forming a fourth heavily doped region of said second type partly in said first well and partly in said second well;
- and
- forming a gate overlying said silicon layer between said second and fourth heavily doped regions wherein said gate comprises a conductive layer overlying said silicon layer with an insulator therebetween wherein said second and third heavily doped regions and said gate are coupled together to form a cathode terminal.
A method to form a LVT-SCR device in the manufacture of an integrated circuit device comprising:
- providing a SOI substrate comprising a silicon layer overlying a buried oxide layer wherein said silicon layer further comprises a first well of a first type and a second well of a second type;
- forming a first heavily doped region of said first type in said second well;
- forming a second heavily doped region of said second type in said first well;
- forming a third heavily doped region of said first type in said first well wherein said second and third heavily doped regions are spaced apart and wherein no other heavily doped region lies between said second and third heavily doped regions;
- forming a fourth heavily doped region of said second type in said first well;
- and
- forming a gate overlying said silicon layer between said second and fourth heavily doped regions wherein said gate comprises a conductive layer overlying said silicon layer with an insulator therebetween, wherein said first and fourth heavily doped regions are coupled together to form an anode terminal and wherein said second and third heavily doped regions and said gate are coupled together to form a cathode terminal.
Dependencies are inferred from the claim text.