Built-in self-repair of semiconductor memory with redundant row testing using background pattern
AssigneeLSI Logic Corporation
InventorsJohnnie A. Huang, Ghasi R. Agrawal
Life of this patent
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Abstract
A method is presented for self-test and self-repair of a semiconductor memory device. Prior to the self-repair stage, both redundant and regular memory portions are comprehensively tested, preferably using a checkerboard bit pattern. Faulty rows identified in each memory portion during testing are recorded. Known-bad rows in regular memory are then replaced by known-good redundant rows in the self-repair stage, and the resulting repaired memory is retested for verification. Compared to existing methods, the new method is believed to provide improved test coverage, making it both more effective in identifying non-repairable memory devices and less prone to fail repairable ones.
Claims24
A method for self-test and self-repair of a semiconductor memory, comprising:
- testing the entirety of a first portion of the memory comprising a matrix of rows and columns, and recording which rows fail the test;
- testing the entirety of a second portion of the memory comprising a matrix of rows and columns, and recording which rows fail the test;
- replacing failed rows in the second portion of memory with rows that did not fail in the first portion;
- and
- testing a third portion of the memory comprising non-failing rows from the second portion, together with replacement rows obtained from the first portion.
A system for self-test and self-repair of a semiconductor memory, said system comprising:
- first portion of the memory, comprising a matrix of rows and columns;
- a second portion of the memory, comprising a matrix of rows and columns;
- test circuitry adapted to test each of the first and second portions and detect rows failing the test, wherein the test circuit is further adapted to test the entirety of each portion;
- and
- repair circuitry adapted to replace failed rows in the second portion with non-failing rows from the first portion.
A computer-usable carrier medium, comprising:
- first program instructions defining operations performable by an execution unit for testing the entirety of a first portion of memory associated with the execution unit, and for recording which rows within the first portion fail the test;
- second program instructions defining operations performable by the execution unit for testing the entirety of a second portion of the memory associated with the execution unit and recording which rows within the second portion fail the test;
- and
- third program instructions defining operations performable by the execution unit for testing a third portion of the memory and recording which rows within the third portion fail the test, wherein said third portion comprises non-failing rows from the first portion and non-failing rows from the second portion.
Dependencies are inferred from the claim text.