Hardware circuitry to speed testing of the contents of a memory

An electronic system, comprising:

• a source of test data, which, if the test data source is operating properly, is a pattern of a limited number of data words successively repeated;
• a memory device for storing the test data;
• and
• a memory test circuit having a memory controller coupled to the source of test data and the memory device for controlling access to the memory device, a pattern memory containing the pattern of data words, a controller coupled to the pattern memory and the memory controller for conditioning the memory controller to write test data from the test data source into the memory device and read test data from the memory device and conditioning the pattern memory to read data words from the pattern memory, and a comparator coupled to the memory controller and the pattern memory for comparing the stored test data to successively repeated pattern data words and generating a signal to indicate whether the stored test data is the same as the successively repeated pattern data words;
• wherein:
• the controller conditions the pattern memory to repeatedly access successive data words in the pattern of data words and simultaneously conditions the memory controller to read successive locations from the memory device, and responds to the compare signal.