Microprocessor with high-reliability operating mode

A computer system comprising:

• a memory to store a plurality of instructions, including a mode switch instruction;
• and
• a processor including
• first and second execution clusters including a first plurality of execution resources and a second plurality of execution resources, respectively, of a plurality of execution units;
• and
• an issue module to provide identical instructions to the first and second execution clusters when the processor is in a first mode and to provide different instructions to the first and second execution clusters when the processor is in a second mode, the processor switching between the first and second processor modes in response to the mode switch instruction.

A computer system comprising:

• a memory to store a plurality of instructions, including a mode switch instruction;
• and
• a processor including
• first and second execution clusters;
• and
• an issue module to provide identical instructions to the first and second execution clusters when the processor is in a first mode and to provide different instructions to the first and second execution clusters when the processor is in a second mode, the processor switching between the first and second processor modes in response to the mode switch instruction, wherein the issue module includes a plurality of slots, the issue module to provide instructions from a first and second of the plurality of slots to the first and second execution clusters when the processor is in the second mode and to provide instructions from the first slot to the both the first and second execution clusters when the processor is in the first mode, wherein the mode switch instruction includes first and second mode switch instructions that set the execution mode status bit to first and second logic states, respectively, when the processor is to switch to the first and second execution modes;
• and
• an execution mode status bit, wherein the issue module provides instructions to the execution clusters according to a logic state of the execution mode status bit.

A computer system comprising:

• a memory to store a plurality of instructions, including a mode switch instruction, and
• a processor including
• first and second execution clusters;
• and
• an issue module to provide identical instructions to the first and second execution clusters when the processor is in a first mode and to provide different instructions to the first and second execution clusters when the processor is in a second mode, the processor switching between the first and second processor modes in response to the mode switch instruction, wherein the mode switch instruction comprises first and second mode switch instructions, the first mode switch instruction to write a first value to the execution mode status bit when the processor is to switch to the first execution mode, and the second mode switch instruction to write a second value to the execution mode status bit when the processor is to switch to the second execution mode;
• and
• an execution mode status bit that indicates to the issue module whether the processor is in the first or second execution mode.

A computer system comprising:

• a memory to store a process thread;
• a processor including:
• first and second execution clusters including a first plurality of execution resources and a second plurality of execution resources, respectively, of a plurality of execution units;
• and
• an issue module to provide identical instructions to the first and second execution clusters when the processor is in a first mode and to provide different instructions to the first and second execution clusters when the processor is in a second mode, the processor to be switched between the first and second modes in response to a mode switch event.