Redundant oscillator and method for generating a regulated signal

A circuit, comprising:

• a signal generator;
• a phase discriminator coupled to the signal generator;
• wherein the signal generator is operable to generate first and second reference signals each having respective zero crossings;
• and
• wherein the phase discriminator is operable to generate a phase-regulated signal having zero crossings that periodically coincide with the zero crossings of one of the first and second reference signals.

A phase-locked loop, comprising:

• a phase detector operable to receive a clock signal having a clock frequency and an oscillator signal having an oscillator frequency and phase and operable to generate an error signal having a signal level that is proportional to the difference between the clock and oscillator frequencies;
• and
• an oscillator coupled to the phase detector and including,
• a signal generator operable to generate a plurality of periodic reference signals such that a majority of the reference signals have a frequency that is proportional to the signal level of the error signal;
• and
• a signal-phase discriminator coupled to the signal generator and operable to generate the oscillator signal such that the oscillator frequency and phase are the same as the frequency and phase of the majority of the periodic reference signals.

A processor, comprising:

• a processing circuit operable to receive a processor clock signal having a processor-clock frequency and a processor-clock phase;
• and
• a phase-locked loop coupled to the processing circuit and operable to receive a system clock signal having a system-clock frequency, the phase-locked loop including,
• a phase detector operable to generate an error signal having a signal level that is proportional to the difference between the system-clock and processor-clock frequencies,
• a signal generator coupled to the phase detector and operable to generate a plurality of periodic reference signals such that a majority of the reference signals have a frequency that is proportional to the signal level of the error signal, and
• a signal-phase discriminator coupled to the signal generator and operable to generate the processor clock signal such that the processor-clock frequency and phase are the same as the frequency and phase of the majority of the periodic reference signals.

An electronic system, comprising:

• a data input device;
• a data output device;
• and
• a computer circuit coupled to the data input and output devices and including a processor that comprises,
• a processing circuit operable to receive a processor clock signal having a processor-clock frequency and a processor-clock phase, and
• a phase-locked loop coupled to the processing circuit and operable to receive a system clock signal having a system-clock frequency, the phase-locked loop including,
• a phase detector operable to generate an error signal having a signal level that is proportional to the difference between the system-clock and processor-clock frequencies,
• a signal generator coupled to the phase detector and operable to generate a plurality of periodic reference signals such that a majority of the reference signals have a frequency that is proportional to the signal level of the error signal, and
• a signal-phase discriminator coupled to the signal generator and operable to generate the processor clock signal such that the processor-clock frequency and phase are the same as the frequency and phase of the majority of the periodic reference signals.

A method, comprising:

• generating three reference signals having respective frequencies and phases;
• equalizing the frequencies and phases of the reference signals;
• and
• generating a regulated signal having the same frequency and phase as a majority of the reference signals if the phases of a minority of the reference signals are unequal to the phase of the majority of the reference signals.