Data processing method and device for parallel stride access

An apparatus for accessing a data element of an N-element data block on N memory locations distributed over Q memory modules via Q parallel accesses, wherein

• said N memory locations are addressable in an n-bit index address, and
• said Q memory modules are addressable in a q-bit module address and an (n−q) bit row address, where N=2n and Q=2q, characterized by:
• means (12), operatively connected to the index address, for selecting (n−q) bits from the index address for providing the row address;
• and
• means (40), operatively connected to the index address, for grouping the index address into a plurality of fields comprising a number of first fields, and for performing a logical function operation on bits obtained from corresponding positions in said plurality of fields for providing the module address for accessing the data elements in said Q memory modules, wherein each of the first fields contains q bits.

A data processing system (100) comprising a memory unit (120) for storing data elements and a data processing module (140), operatively connected to the memory unit for accessing the data elements, wherein the memory unit comprises an N-element data block in N memory locations addressable in an n-bit index address (20), with N=2n, characterized in that

• the N-element data block on N memory locations is distributed over Q memory modules (1200, . . . , 120Q−1), wherein the Q memory modules are addressable in a q-bit module address (M) and an (n−q) bit row address (R), with Q=2q;
• the data processing module comprises Q data processors (1420, . . . , 142Q−1), adapted to accessing the Q memory modules via Q parallel accesses;
• said system further characterized by
• an address generator (100), operatively connected to the memory unit, for providing access to the data elements in the memory unit, wherein the address generator comprises:
• a first address generator (12), operatively connected to the index address (20), for providing the row address (R);
• and
• a second address generator (40), operatively connected to the index address (20), for providing the module address (M), and
• an interconnector means (130, 132), operatively connected to the address generator (100), the memory unit 120 and the data processor module 140, for allowing the Q data processors to access the data elements in the Q memory modules, wherein
• the row address provided by the first address generator (20) is selected from (n−q) bits of the index address, and
• the module address provided by the second address generator is obtained by:
• grouping the index address (20) into a plurality of fields comprising a number of first fields, each first field containing q bits;
• and
• performing a logical function operation on bits obtained from corresponding position in said plurality of fields.