Apparatus and method of utilizing Alias Hit signals to detect errors within the real address tag arrays
AssigneeInternational Business Machines Corporation
InventorsJose Angel Paredes, Bruce Joseph Ronchetti, Binta Minesh Patel, George McNeil Lattimore
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Abstract
A data processing system including a processor having a load/store unit and method for utilizing alias hit signals to detect errors within the read address tag arrays. Within a load store unit, implemented within a processor, a real address tag array is utilized to indicate when effective address aliasing occurs in a primary cache array. If aliasing occurs, Alias Hit signals are then used to clear any aliased entries. These Alias Hit signals can also be utilized to determine if there has been some type of failure within the real address tag array.
Claims15
A processor comprising a load/store unit having a primary cache and adaptable for coupling to a memory subsystem, the load/store unit further comprising:
- a first set of real address tag arrays operable for correcting effective address aliasing within the load/store unit;
- first comparators for comparing a received real address to real addresses in each of the real address tag arrays in the first set;
- first circuitry for determining if there is a hit in each of the real address tag arrays in the first set as a result of the comparing of the received real address to the real addresses in each of the real address tag arrays in the first set;
- and
- first circuitry for reporting an error in circuitry associated with the first set of real address tag arrays if the first determining circuitry outputs more than one hit signal.
A method for discovering errors in a load/store unit comprising the steps of:
- comparing a received real address to real addresses in each of a first set of real address tag arrays;
- determining if there is a hit in each of the real address tag arrays in the first set as a result of the comparing of the received real address to the real addresses in each of the real address tag arrays in the first set;
- and
- reporting an error in circuitry associated with the first set of real address tag arrays if the determining step outputs more than one hit signal.
A load/store unit having a primary cache and adaptable for coupling to a memory subsystem, the load/store unit further comprising:
- a first set of real address tag arrays operable for correcting effective address aliasing within the load/store unit;
- first comparators for comparing a received real address to real addresses in each of the real address tag arrays in the first set;
- first circuitry for determining if there is a hit in each of the real address tag arrays in the first set as a result of the comparing of the received real address to the real addresses in each of the real address tag arrays in the first set;
- and
- first circuitry for reporting an error in circuitry associated with the first set of real address tag arrays if the first determining circuitry outputs more than one hit signal.
Dependencies are inferred from the claim text.