Scalable multiprocessor system and cache coherence method incorporating invalid-to-dirty requests

A multiprocessor computer system including a plurality of nodes, each node including

• an interface to a local memory subsystem, the local memory subsystem storing a multiplicity of memory lines of information and a directory;
• a memory cache for caching a multiplicity of memory lines of information, including memory lines of information stored in a remote memory subsystem that is local to another node;
• a protocol engine implementing a negative acknowledgment free cache coherence protocol, the protocol engine including
• a memory transaction array for storing an entry related to a memory transaction, the entry including a memory transaction state, the memory transaction concerning a memory line;
• logic for processing the memory transaction, including advancing the memory transaction when predefined criteria are satisfied and storing a state of the memory transaction in the memory transaction array;
• the protocol engine configured to support an invalid-to-dirty memory transaction, wherein
• the protocol engine included in a first node from the plurality of nodes is configured to sends an invalid-to-dirty request to a second node from the plurality of nodes, said invalid-to-dirty request identifying a memory line of information stored in the remote memory subsystem that is local to the second node;
• the protocol engine included in the second node is configured to send an invalid-to-dirty invalidation request to a third node from the plurality of nodes in response to the invalid-to-dirty request if the third node has previously been designated as exclusive owner of the memory line;
• the protocol engine included in the second node is configured to designate the first node as exclusive owner of the memory line of information in response to the invalid-to-dirty request;
• the protocol engine included in the third node is configured to respond to the invalid-to dirty invalidation request by invalidating a copy of the memory line of information cached in the memory cache in response to the invalid-to-dirty invalidation request and sending an invalid-to-dirty invalidation reply to the first node.