Input staging logic for latching source synchronous data

A Peripheral Component Interconnect (PCI) compatible device including a circuit arrangement configured to receive a source synchronous data signal and first and second complementary source synchronous data strobe signals from a PCI compatible bus, the circuit arrangement comprising:

• (a) first and second source synchronous latches, each source synchronous latch including a data input, a data output, and a clock input, the data input of each source synchronous latch configured to receive the data signal, the clock input of the first source synchronous latch configured to receive the first data strobe signal, and the clock input of the second source synchronous latch configured to receive the second data strobe signal;
• (b) sequencer logic including first and second portions, each portion configured to output a plurality of staging strobe signals, the first and second portions respectively clocked by the first and second data strobe signals;
• (c) a first plurality of staging register latches including six staging register latches, each staging register latch in the first plurality of staging register latches including a data input coupled to the data output of the first source synchronous latch, a data output, and a clock input configured to receive one of the plurality of staging strobe signals output by the first portion of the sequencer logic;
• (d) a second plurality of staging register latches including six staging register latches, each staging register latch in the second plurality of staging register latches including a data input coupled to the data output of the second source synchronous latch, a data output, and a clock input configured to receive one of the plurality of staging strobe signals output by the second portion of the sequencer logic;
• and
• (e) a common clock synchronizing circuit coupled to the data outputs of the staging register latches in the first and second pluralities of staging register latches, the common clock synchronizing circuit including a plurality of common clock synchronized latches, wherein the common clock synchronized circuit is configured to sequentially latch into the plurality of common clock synchronized latches the data outputs of selected staging register latches from the first and second pluralities of staging register latches responsive to a common clock signal.

A circuit arrangement, comprising:

• (a) source synchronous input staging logic configured to receive a source synchronous data signal, the input staging logic including:
• (i) first and second latching stages respectively configured to store a plurality of data values from first and second data phases of the source synchronous data signal, the first latching stage including first and second staging register latches, the second staging register latch configured to receive data from a later sub-phase of the first data phase than the first staging register latch;
• and
• (ii) sequencer logic coupled to the first and second latching stages and configured to sequentially route data values from the source synchronous data signal to the first and second latching stages at least in part by selectively gating the first and second staging register latches;
• and
• (b) a common clock synchronizing circuit coupled to the input staging logic and configured to synchronize data from the source synchronous data signal to a common clock signal by sequentially latching data values from the first and second latching stages;
• wherein the input staging logic further includes at least one supplemental holding latch coupled intermediate an output of the first staging register latch and the common clock synchronizing circuit, the supplemental holding latch gated by the sequencer logic to latch the output of the first staging register latch concurrently with gating of the second staging register latch.

A method of receiving a source synchronous data signal, the method comprising:

• (a) in response to at least one source synchronous data strobe signal, latching a plurality of data values from each of first and second data phases of the source synchronous data signal into first and second latching stages, respectively, wherein latching the data values from the first data phase into the first latching stage includes:
• (i) latching a first data value into a first staging register latch during a first sub-phase of the first data phase;
• (ii) latching a second data value into a second staging register latch during a second sub-phase of the first data phase;
• and
• (iii) concurrently with latching the second data value into the second staging register latch, latching the first data value into a supplemental holding latch coupled to an output of the first staging register latch;
• and
• (b) synchronizing the plurality of data values from the first and second data phases with a common clock by sequentially latching in response to a common clock signal the data values latched into each of the first and second latching stages.