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US 6,640,267 B1Granted
Architecture for multi-queue storage element
AssigneeCypress Semiconductor Corporation
InventorS. Babar Raza
Life of this patent
Estimating the term…
Abstract
A circuit comprising a memory and a logic circuit. The memory may be configured to read and write data in a plurality of memory queues to/from a write data path and a read data path in response to (i) a first and a second select signal and (ii) a first control signal. The logic circuit may be configured to generate (i) the first and second select signals and (ii) the control signal in response to one or more signals received from a read management path and/or a write management path.
Claims20
A circuit comprising:
- a memory configured to store data in a plurality of memory queues, wherein said data is (i) written to said plurality of memory queues from a write data path and (ii) read from said plurality of memory queues to a read data path in response to a first select signal, a second select signal and a first control signal;
- and
- a logic circuit configured to generate (i) said first and second select signals and (ii) said first control signal in response to one or more second control signals received from a read management path and/or a write management path.
A circuit comprising:
- means for storing data in a plurality of memory queues, wherein said data is (i) written to said plurality of memory queues from a write data path and (ii) read from said plurality of queues to a read data path in response to a first select signal, a second select signal and a first control signal;
- and
- means for generating (i) said first and second select signals and (ii) said first control signal in response to one or more second control signals received from a read management path and/or a write management path.
A method for storing data in a memory comprising the steps of:
- (A) writing data to a plurality of memory queues from a write data path and reading data from said plurality of memory queues to a read data path in response to (i) a first select signal, (ii) a second select signal and (iii) a first control signal;
- and
- (B) generating (i) said first and second select signals and (ii) said first control signal in response to one or more second control signals received from a read management path and/or a write management path.
Dependencies are inferred from the claim text.