Method and device for performing write operations to synchronous burst memory
AssigneeCypress Semiconductor Corporation
InventorsMathew R. Arcoleo, Rajesh Manapat, Scott Harmel
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Abstract
A device generally comprising a memory array and a burst sequence generator. The memory array may be configured to store data. The burst sequence generator may be configured to generate a burst sequence in response to address information received by the device. The burst sequence may be configured to identify a plurality of locations for storing data in the memory array. The device may have a maximum operating current of 50 milliamps and/or a maximum standby current of about 25 microamps.
Claims20
A device, comprising:
- a memory array;
- and
- a circuit configured to (i) conduct a single write operation to said memory array in response to an enable signal being asserted and while a control signal is being deasserted, (ii) continue said single write operation as a burst write operation while said enable signal is deasserted and said control signal is asserted said (iii) end said burst write operation in response to said enable signal being deasserted and said control signal deasserted.
A method for reading and writing, comprising the steps of:
- (A) conducting a single write operation to a memory array in response to an enable signal being asserted and while a control signal is being deasserted;
- (B) continuing said single write operation as a burst write operation while said enable signal is deasserted and said control signal is asserted;
- and
- (C) ending said burst write operation in response to said enable signal being deasserted and said control signal being deasserted.
A device comprising:
- means for conducting a write operation to a memory array in response to an enable signal being asserted and while a control signal is being deasserted;
- means for continuing said single write operation as a burst write operation while said enable signal is deasserted and said control signal is asserted;
- and
- means for ending said burst write operation in response to said enable signal being deasserted and said control signal being deasserted.
Dependencies are inferred from the claim text.