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AssigneeQUALCOMM Incorporated
InventorsEdward O. Lupin, Nagabhushana T. Sindhushayana
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The invention presented is a novel method and apparatus for generating PN sequences with an arbitrary number of bits, where the number of bits is provided in parallel with each clock pulse. This allows the sequences to be generated at high speed when needed, and allows parallel processing in the acquisition and demodulation processes. In the invention, the initial values of states are loaded into registers of a parallel PN generator, which immediately generates the next n bits of the PN sequence, where n is an arbitrary number dependent on performance required. Then, a first sub-part of the PN generator of the present invention receives the present state of the PN generator and outputs the state of the PN generator n bits in the future. The output of this first sub-part is then provided to a second sub-part of the generator, which generates the next n bits of the PN sequence. In this fashion, the entire PN sequence can be continuously generated. The PN generator also contains a control processor, coordinating co-operation between sub-systems.
An apparatus for generating multiple bits of a pseudonoise sequence by computing the bits in parallel, comprising:
A pseudonoise (PN) sequence generator comprising:
A method for generating multiple bits of a pseudonoise sequence by computing the bits in parallel, comprising the steps of:
Dependencies are inferred from the claim text.