Timing jitter frequency detector for timing recovery systems

A timing recovery system, comprising:

• a phase detector to receive an input phase signal and an output phase signal, wherein the phase detector outputs a phase error based on the input phase signal and the output phase signal;
• a loop filter to receive and filter the phase error from the phase detector and to output a control signal based on the filtered phase error;
• an oscillator to receive the control signal from the loop filter and to create a recovered clock as the output phase signal to provide to the phase detector;
• and
• a frequency detector having
• a slicer to receive and slice the phase error against a compare threshold value, and to generate a symbol based on the phase error sliced against the compare threshold value,
• a symbol counter to increment a symbol count if the symbol generated is same as a last symbol,
• a logic circuit to compare the symbol count with a symbol count limit if the symbol is different from the last symbol, to increment a high counter and clear a low counter if the symbol count is less than the symbol count limit, and to increment the low counter and clear the high counter if the symbol count is greater than the symbol count limit;
• and
• a combinational logic circuit to generate a high frequency jitter true signal or a high frequency jitter false signal for the phase detector and the loop filter based on at least one of the symbol count, the high counter, and the low counter.

A method of operating a frequency detector, comprising:

• slicing a phase error against a compare threshold value;
• generating a symbol based on the phase error sliced against the compare threshold value;
• incrementing a symbol count if the symbol generated is same as a last symbol;
• comparing the symbol count with a symbol count limit if the symbol is different from the last symbol;
• incrementing a high counter and clearing a low counter if the symbol count is less than the symbol count limit after comparing the symbol count with the symbol count limit;
• incrementing the low counter and clearing the high counter if the symbol count is greater than the symbol count limit after comparing the symbol count with the symbol count limit;
• and
• generating a high frequency true signal or a high frequency jitter false signal based on at least one of the symbol count, the high counter, and the low counter.

A frequency detector, comprising:

• a machine-readable storage medium;
• and
• machine-readable program code, stored on the machine-readable storage medium, having instructions to
• slice a phase error against a compare threshold value;
• generate a symbol based on the phase error sliced against the compare threshold value;
• increment a symbol count if the symbol generated is same as a last symbol;
• compare the symbol count with a symbol count limit if the symbol is different from the last symbol;
• increment a high counter and clear a low counter if the symbol count is less than the symbol count limit after the symbol count is compared with the symbol count limit;
• increment the low counter and clear the high counter if the symbol count is greater than the symbol count limit after the symbol count is compared with the symbol count limit;
• and
• generate a high frequency true signal or a high frequency jitter false signal based on at least one of the symbol count, the high counter, and the low counter.