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US 6,639,958 B1Granted
Circuit configuration for the interference-free initialization of delay locked loop circuits with fast lock
AssigneeInfineon Technologies AG
InventorsRainer Höhler, Mathias Von Borcke
Life of this patent
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Abstract
The invention relates to a circuit configuration for the interference-free initialization of delay locked loop circuits with fast lock. A control signal for rapidly adjusting the DLL circuit is converted into a delayed control signal, which is kept constant with the rising edge of a counter clock signal. This prevents instabilities of the counter value from occurring.
Claims9
A circuit configuration for the interference-free initialization of delay locked loop circuits with fast lock, which comprises:
- a delay line receiving an external clock signal and outputting an on-chip clock signal;
- a phase detector, a filter, a counter device and an analog/digital converter connected to and driving said delay line for synchronizing the on-chip clock signal with the external clock signal;
- said counter device having at least one higher-order counter and a lower-order counter each triggered by a counter clock signal and alternatively activatable and deactivatable with a control signal for shortening a time taken to adjust the delay locked loop;
- wherein the control signal is converted into a delayed control signal and kept constant with a rising edge of the counter clock signal.
1 more element
Dependencies are inferred from the claim text.