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US 6,639,956 B1Granted
Data resynchronization circuit
AssigneeIntel Corporation
InventorHongjiang Song
Life of this patent
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Abstract
An apparatus comprising three sampling circuits to sample incoming data and a quarter clock. A clock generation unit is included to generate at least three sampling clocks from a local clock. Each of the three sampling clocks are configured to sample the incoming data and the quarter clock. A phase detector is also included to detect a phase difference between the quarter clock and the local clock and to generate a recovered quarter clock. A delay line is further included to delay the sampled incoming data and the recovered quarter clock by the detected phase difference.
Claims21
An apparatus comprising:
- at least two sampling circuits to sample incoming data and a first clock:
- a clock generation unit to generate a plurality of sampling clocks from a second clock, the plurality of sampling clocks used by the sampling circuits to sample the incoming data and the first clock;
- a phase detector to detect a phase difference between the first clock and the second clock;
- and
- a delay line to delay the sampled incoming data based on the detected phase difference, wherein the delay line delays the sampled incoming data by selecting one of sampled data points of the sampled incoming data,
- wherein the phase detector comprises a state machine that issues control signals to the delay line based on the current state of the state machine and a receiving input from a plurality of sample points of one of the sampling circuits.
3 more elements
An apparatus comprising:
- at least two sampling circuits to sample incoming data and a first clock;
- a clock generation unit to generate a plurality of sampling clocks from a second clock, the plurality of sampling clocks used by the sampling circuits to sample the incoming data and the first clock;
- a phase detector to detect a phase difference between the first clock and the second clock;
- and
- a delay line to delay the sampled incoming data based on the detected phase difference, wherein the delay line delays the sampled incoming data by selecting one of sampled data points of the sampled incoming data,
- wherein a first sampling circuit of the at least two sampling circuits is an oversampling circuit to oversample incoming data captured by a clock rising edge,
- a second sampling circuit of the at least two sampling circuits is an oversampling circuit to oversample incoming data captured by a clock falling edge, and
- a third sampling circuit of the at least two sampling circuits is an oversampling circuit to oversample the first clock.
5 more elements
An apparatus comprising:
- at least two sampling circuits to sample incoming data and a first clock;
- a clock generation unit to generate a plurality of sampling clocks from a second clock, the plurality of sampling clocks used by the sampling circuits to sample the incoming data and the first clock;
- a phase detector to detect a phase difference between the first clock and the second clock;
- and
- a delay line to delay the sampled incoming data based on the detected phase difference, wherein the delay line delays the sampled incoming data by selecting one of sampled data points of the sampled incoming data,
- wherein the delay line comprises a fine digital delay line and a coarse digital delay line.
3 more elements
A method of data resynchronization comprising:
- (a) sampling incoming data and a first clock;
- (b) generating at least three sampling clocks from a second clock, each of the three sampling clocks to sample the incoming data and the first clock;
- (c) detecting a phase difference between the first clock and the second clock;
- and
- (d) delaying the sampled incoming data based on the detected phase difference by selecting one of sampled data points of the sampled incoming data,
- repeating (a) through (d) a plurality of times, wherein sampling a first time comprises oversampling incoming data captured by a clock rising edge;
- sampling a second time comprises oversampling incoming data captured by a clock falling edge;
- and
- sampling a third time comprises oversampling the first clock.
6 more elements
A method of data resynchronization comprising:
- (a) sampling incoming data and a first clock;
- (b) generating at least three sampling clocks from a second clock, each of the three sampling clocks to sample the incoming data and the first clock;
- (c) detecting a phase difference between the first clock and the second clock;
- and
- (d) delaying the sampled incoming data based on the detected phase difference by selecting one of sampled data points of the sampled incoming data,
- wherein delaying comprises fine digital delaying and coarse digital delaying.
3 more elements
A system comprising:
- a processor;
- and
- a peripheral controller coupled to the processor, the processor adapted to access data from the peripheral controller, the peripheral controller comprising:
- a decoder to receive data signal and strobe signal and generate a first data signal, a second data signal and a recovered clock signal;
- a first sampling circuit to oversample the first data signal generated by the decoder;
- a second sampling circuit to oversample the second data signal generated by the decoder;
- and
- a third sampling circuit to oversample the recovered clock signal generated by the decoder;
- a clock generation unit to generate at least three sampling clocks from a local clock, each of the three sampling clocks used by the sampling circuits to sample the first and second data signals and the recovered clock signal;
- a phase detector to detect a phase difference between the recovered clock signal and the local clock;
- and
- a delay line to delay the sampled data signals based on the detected phase difference, wherein the delay line delays the sampled incoming data by selecting one of sampled data points of the sampled incoming data.
9 more elements
Dependencies are inferred from the claim text.