Demodulator synchronization loop lock-in detection circuit

A machine-readable medium encoded with a program for detecting the lock-in of a loop that synchronizes an internal clock on the transmission of value pairs, said program containing instructions for performing the steps of:

• calculating a module of a vector that has as components the values of one of the value pairs;
• comparing the module with a threshold;
• and
• determining the locked-in condition according to the ratio of the number of modules found to be greater than or smaller than the threshold to a total number of modules.

A lock-in detection circuit for detecting the lock-in of a loop that synchronizes an internal clock on the transmission of value pairs provided by a demodulator, said lock-in detection circuit comprising:

• a calculation circuit for calculating a module of a vector that has as components the values of one of the value pairs;
• a register storing a threshold;
• a comparator for comparing the threshold stored in the register with the module calculated by the calculation circuit, the comparing generating a comparison result;
• a modification circuit for modifying the threshold stored in the register based on the comparison result;
• and
• an analysis circuit for analyzing the threshold stored in the register to determine a locked-in condition.