Address transition detecting circuit
AssigneeHynix Semiconductor Inc.
InventorTae Seung Sin
Life of this patent
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Abstract
The present invention relates to an address transition detecting circuit. The present invention has a control means for control charge/discharge of a given portion of the address transition detecting circuit in order to remove a noise of an address transition detection signal generated by a glitch signal included in a given signal applied to an input terminal of an address transition detecting circuit and also has a noise removing circuit for removing the noise included in the address transition detection signal in the output unit of the address transition detecting circuit. Therefore, the present invention can prevent generation of an unnecessary address transition detection signal pulse upon generation of a glitch and can thus stably drives semiconductor chips even at a high power supply voltage.
Claims17
An address transition detecting circuit, comprising:
- a first detecting means for detecting a first transition of an address buffer signal and outputting an external address signal having a first phase and a first pulse width;
- a first control means for controlling a flow of current of the first detecting means so that the output of the first detecting means has a second phase different from the first phase and a second pulse width equal to the first pulse width;
- a second detecting means for detecting a second transition of the address buffer signal;
- a second control means for controlling a flow of current of the second detecting means so that an output of the second detecting means has a third phase different from the first phase and a third pulse width equal to the first pulse width;
- and
- an output means for inverting one of the output of the first detecting means and the output of the second detecting means to output an address transition detecting signal.
An address transition detecting circuit, comprising:
- a first detecting means for detecting a first transition of an address buffer signal and outputting an external address signal having a first phase and a first pulse width;
- a first control means for controlling a flow of current of the first detecting means so that the output of the first detecting means has a second phase different from the first phase and a second pulse width equal to the first pulse width;
- a second detecting means for detecting a second transition of the address buffer signal;
- a second control means for controlling a flow of current of the second detecting means so that an output of the second detecting means has a third phase different from the first phase and a third pulse width equal to the first pulse width;
- a first output means for inverting one of the output of the first detecting means and the output of the second detecting means to output a first address transition detecting signal;
- a noise removing means for removing a noise included in the first address transition detecting signal;
- and
- a second output means for inverting an output of the noise removing means to output a second address transition detecting signal.
Dependencies are inferred from the claim text.