Clock-synchronous semiconductor memory device

A semiconductor device comprising:

• a memory cell array having a plurality of memory cells arranged in rows and columns;
• a counting circuit configured to receive a clock signal and counting a number of clock cycles of the clock signal;
• a control circuit configured to receive an external control signal, and to generate an internal control signal on the basis of the external control signal and/or an output signal from the counting circuit;
• a specification circuit configured to receive address signals in response to the internal control signal generated from the control circuit, and to designate a memory cell in said memory cell array;
• a selection circuit configured to receive the address signals in response to the internal control signal from said control circuit, and to select one of a normal operation mode and a synchronous mode in a mode setting cycle;
• and
• a data I/O circuit configured to input data into the memory cell selected by said specification circuit and to output the data from the memory cell selected by said specification circuit,
• wherein in the normal mode, setting of address signals of the memory cell in said memory cell array by the specification circuit is effected irrespective of the clock signal, and in the synchronous mode, a rising edge or a falling edge of the clock signal determines a setting timing of the address signals of the memory cell in said memory cell array by the specification circuit.