Decoder circuit in a semiconductor memory device
AssigneeHynix Semiconductor Inc.
InventorYoung Bo Shim
Life of this patent
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Abstract
A decoder circuit in a semiconductor memory device for improving the productivity of a semiconductor memory device by reducing the area occupied by a decoder. In order to accomplish this, a decoder circuit in a semiconductor memory device comprises a decoder control unit for receiving an external clock signal and a reset signal to generate a clear signal, an internal reset signal, a plurality of driver enable signals and a plurality of shift register enable signals; and a plurality of decoders for decoding the clear signal, the internal reset signal, the plurality of driver enable signals and the plurality of shift register enable signals to generate a plurality of wordline-driving signals.
Claims22
A decoder circuit in a semiconductor memory device, the decoder circuit comprising:
- a decoder control means for outputting a plurality of control signals in response to an external clock signal and a reset signal;
- and
- a plurality of decoders each of which drives a plurality of word lines in response to the plurality of control signals, an output node of one decoder being connected to an input node of an adjacent decoder and an output node of a last decoder being connected to an input node of a first decoder.
A decoder circuit in a semiconductor memory device, the decoder circuit comprising:
- a decoder control means for generating an internal reset signal, a plurality of driver enable signals and a plurality of shift register enable signals in response to an external clock signal and a reset signal;
- a plurality of shift registers for generating a plurality of latch signals in response to the internal reset signal and the plurality of shift register enable signals;
- and
- a plurality of drivers for driving a plurality of wordlines in response to the plurality of latch signals and the plurality of driver enable signals,
- wherein the plurality of shift registers has a loop structure in which an output signal of the shift register at the last stage of the plurality of shift registers is inputted to an input terminal of the shift register at the first stage of the plurality of shift registers.
A decoder circuit in a semiconductor memory device comprising:
- a plurality of decoders;
- a decoder control means for controlling the plurality of decoders in response to an external clock signal and a reset signal, said plurality of decoders driving a plurality of word lines in response to output signals from said decoder control means;
- said decoder control means including,
- a clear signal generator for receiving the external clock signal and an inverted signal of the reset signal to generate first and second internal clock signals and a clear signal;
- an internal reset signal generator for receiving the reset signal to generate an internal reset signal;
- an assembled latch circuit for generating a plurality of latch signals in response to the first and the second internal clock signals and the internal reset signal;
- and
- a shift register/driver enable signal generator for receiving the plurality of latch signals to generate a plurality of driver enable signals and a plurality of shift register enable signals.
Dependencies are inferred from the claim text.