Memory device, method of accessing the memory device, and reed-solomon decoder including the memory device
AssigneeSamsung Electronics Co., Ltd.
InventorHyung Joon Kwon
Life of this patent
Estimating the term…
Abstract
A memory device employs multiple dual-bank RAMs to allow simultaneous write/read operations. The memory may be utilized in a high-speed block pipelined Reed-Solomon decoder for temporarily storing input codewords during pipelined processing. A memory controller enables writing to and reading from the dual-bank RAMs during each of successive frame periods such that each bank of the dual-bank RAMs is read every given number of frame periods and is written every same given number of frame periods, and such that a read bank is contained in a different one of the dual-bank RAMs than is a write bank in each of the successive frame periods.
Claims20
A buffer circuit for simultaneous writing and reading of data during each of successive frame periods, comprising:
- a plurality of dual-bank RAMs;
- and
- a memory control circuit, coupled to said plurality of dual-bank RAMs, which enables writing to and reading from said plurality of dual-bank RAMs during each of the successive frame periods such that each bank of the dual-bank RAMs is read every given number of frame periods and is written every said given number of frame periods, and such that a read bank is contained in a different one of said plurality of dual-bank RAMs than is a write bank in each of the successive frame periods.
A buffer circuit for simultaneous writing and reading of data during each of successive frame periods, comprising:
- a first dual-bank RAM having a first bank and a second bank;
- a second dual-bank RAM having a third bank and a fourth bank;
- a third dual-bank RAM having a fifth bank and a sixth bank;
- and
- a memory control circuit, coupled to said first, second and third dual-bank RAMs, which enables reading from said first through sixth data banks in order during the successive frame periods such that each one of said first through sixth data banks is read every six frame periods, and which enables writing to said first through sixth data banks in order during the successive frame periods such that each one of said first through sixth data banks is written every six frame periods;
- wherein, during each of said frame periods, a one of said first through sixth data banks for which reading is enabled by said memory control circuit is contained in a different one of said first through third dual-bank RAMs than is a one of said first through sixth data banks for which writing is enabled by said memory control circuit.
A method for accessing a plurality of dual-bank memories, said method comprising enabling writing to and reading from the plurality of dual-bank memories during each of successive frame periods such that each bank of the dual-bank memories is read every given number of frame periods and is written every said given number of frame periods, and such that a read bank is contained in a different one of the plurality of dual-bank memories than is a write bank in each of the successive frame periods.
A method for accessing a memory device containing a first dual-bank RAM having a first bank and a second bank, a second dual-bank RAM having a third bank and a fourth bank, and a third dual-bank RAM having a fifth bank and a sixth bank, said method comprising:
- enabling reading from the first through sixth data banks in order during successive frame periods such that each one of said first through sixth data banks is read every six frame periods;
- and
- enabling writing to said first through sixth data banks in order during the successive frame periods such that each one of said first through sixth data banks is written every six frame periods;
- wherein, during each of said frame periods, a one of said first through sixth data banks for which reading is enabled is contained in a different one of said first through third dual-bank RAMs than is a one of said first through sixth data banks for which writing is enabled.
A pipelined Reed-Solomon decoder, comprising:
- a plurality of pipelined processing units which receive input Reed-Solomon codewords and which executed computations to identify error locations and error values contained in the input codewords;
- and
- a buffer circuit which temporarily stores the input codewords during execution of the computations by the plurality of pipelined processing units;
- wherein the buffer circuit comprises:
- a plurality of dual-bank RAMs;
- and
- a memory control circuit, coupled to said plurality of dual-bank RAMs, which enables writing to and reading from said plurality of dual-bank RAMs during each of the successive frame periods such that each bank of the dual-bank RAMs is read every given number of frame periods and is written every said given number of frame periods, and such that a read bank is contained in a different one of said plurality of dual-bank RAMs than is a write bank in each of the successive frame periods.
A pipelined Reed-Solomon decoder, comprising:
- a plurality of pipelined processing units which receive input Reed-Solomon codewords and which executed computations to identify error locations and error values contained in the input codewords;
- and
- a buffer circuit which temporarily stores the input codewords during execution of the computations by the plurality of pipelined processing units;
- wherein the buffer circuit comprises:
- a first dual-bank RAM having a first bank and a second bank;
- a second dual-bank RAM having a third bank and a fourth bank;
- a third dual-bank RAM having a fifth bank and a sixth bank;
- and
- a memory control circuit, coupled to said first, second and third dual-bank RAMs, which enables reading from said first through sixth data banks in order during the successive frame periods such that each one of said first through sixth data banks is read every six frame periods, and which enables writing to said first through sixth data banks in order during the successive frame periods such that each one of said first through sixth data banks is written every six frame periods;
- wherein, during each of said frame periods, a one of said first through sixth data banks for which reading is enabled by said memory control circuit is contained in a different one of said first through third dual-bank RAMs than is a one of said first through sixth data banks for which writing is enabled by said memory control circuit.
Dependencies are inferred from the claim text.