Semiconductor memory device having defective memory block

Abstract

A semiconductor memory such as 256 KB-memory has a memory cell array divided into a plurality of memory blocks, and a defective memory block exists in the memory cell array. In this case, to relive the 256 KB-memory as a 192 KB-memory not including the defective memory block of 64 KB, identification information identifying the defective memory block is stored in a relief condition storing unit, an address sent from an address bus is changed according to the identification information, and a changed address is input to a decoder of the memory cell array. For example, because a memory block of an address (0, 0) is not guaranteed, in cases where a physical address (0, 1) is assigned to the defective memory block, the address change is performed to change an address (0, 0) sent from the address bus to the address (0, 1 ) of the defective memory block.

Dependencies are inferred from the claim text.