Memory chip having a test mode and method for checking memory cells of a repaired memory chip
AssigneeInfineon Technologies AG
InventorsPeter Beer, Carsten Ohlhoff
Life of this patent
Estimating the term…
Abstract
The memory chip has regular memory cells and standby memory cells for replacing faulty memory cells. There is provided a method for checking memory cells of a repaired memory chip, where the memory cells are checked by putting the memory chip into the state before repair. This actuates the memory cells identified as being faulty in spite of the provision of standby memory cells. This allows the operability of the memory chip to be checked after the repair procedure has been carried out. It is thus possible to identify, by way of example, whether a fault has been produced by the repair procedure.
Claims7
A memory chip, comprising:
- a plurality of memory cells;
- an address circuit connected to address lines for supplying an address to said memory cells via selection lines for activating respective said memory cells;
- said address circuit, upon receiving an address on the address lines, activating a prescribed memory cell via said selection lines, to enable a data item to be read from or to be written to said memory cell;
- standby memory cells connected to said address circuit via further selection lines;
- a first address memory connected to said address circuit for storing addresses for faulty memory cells;
- said address circuit comparing a prescribed address with the addresses in said first address memory and, if the prescribed address is held in said first address memory, activating a respective said standby memory cell instead of said faulty memory cell;
- a test circuit connected to said address circuit, and outputting a signal to the address circuit in a test mode;
- and
- if the signal is present and an address for a faulty memory cell is applied, said address circuit activating said faulty memory cell instead of the respective said standby memory cell.
In a method of checking memory cells of a repaired memory chip, where a memory cell is stipulated by the presentation of an address, and the memory cell associated with the address is activated for writing or reading a data item, where a repair procedure for a memory cell identified as being faulty stipulates a standby memory cell which, upon presentation of the address of the faulty memory cell, is activated instead of the faulty memory cell, the improvement which comprises:
- activating the faulty memory cell instead of the standby memory cell when a test signal has been presented.
Dependencies are inferred from the claim text.