Semiconductor device having a defect relief function of relieving a failure
AssigneeFujitsu Limited
InventorKazuto Furumochi
Life of this patent
Estimating the term…
Abstract
A first and second semiconductor memory circuits and a redundant circuit for realizing a defect relief function are made connectable, whereby the redundant circuit is shared between the two semiconductor memory circuits, and when a failure occurs in either of the semiconductor memory circuits, the redundant circuit operates as a portion in the semiconductor memory circuit. Consequently, the defect relief function can be added to each of the two semiconductor memory circuits by only adding one redundant circuit and redundant changeover switch groups.
Claims24
A semiconductor device, comprising:
- a plurality of semiconductor memory circuits respectively operating based on different address signals and capable of storing data;
- and
- a redundant circuit shared between the plurality of semiconductor memory circuits, for relieving a failure in the semiconductor memory circuits,
- wherein the redundant circuit is allowed to operate as a portion in any one of the semiconductor memory circuits in accordance with redundant information on the plurality of semiconductor memory circuits, and
- wherein the plurality of semiconductor memory circuits and the redundant circuit are connected to one another via a plurality of switching circuits for sending and receiving control signals obtained by decoding the plural different address signals respectively and inputted/outputted data.
A semiconductor device, comprising:
- a plurality of semiconductor memory circuits respectively operating based on different address signals and capable of storing data;
- and
- a redundant circuit shared between the plurality of semiconductor memory circuits, for relieving a failure in the semiconductor memory circuits,
- wherein the redundant circuit is allowed to operate as a portion in any one of the semiconductor memory circuits in accordance with redundant information on the plurality of semiconductor memory circuits, and
- wherein, when a signal line in the redundant circuit is in an inactive state, a given electric potential is supplied to the signal line.
Dependencies are inferred from the claim text.