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US 6,639,854 B2Granted
Redundancy circuit of semiconductor memory device
AssigneeHynix Semiconductor Inc.
InventorsYoung Do Hur, Jong Chern Lee
Life of this patent
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Abstract
A semiconductor memory device having a redundancy circuit, includes a normal memory cell array unit, a redundancy memory cell array unit for recovering defective cells of the normal memory cell array unit, and a memory driving unit for operating the normal memory cell adjacent to the redundancy memory cell array unit immediately after a word line move time ‘tcycle’ is elasped by using address data.
Claims32
A semiconductor memory device having a redundancy circuit, the device comprising:
- a normal memory cell array unit;
- a redundancy memory cell array unit for recovering defective cells of the normal memory cell array unit;
- a test mode signal generating unit for generating a test mode signal indicating a test operation;
- a row address counter unit for receiving the test mode signal, a first signal enabled in a refresh mode and a second signal toggling once in a refresh mode and for generating a row address counter signal;
- a row counter reset unit for receiving the test mode signal and a part of the row address counter signal and for generating a reset signal to reset the row address counter unit;
- a row counter reset initialization unit for receiving the test mode signal and for generating an initialization signal to initialize the row counter reset unit;
- a row address buffer unit for receiving the row address counter signal and a row address signal from a general address buffer and for generating a row address data signal;
- row predecoder and decoder units for receiving the row address data signal and for generating a signal to select word lines of the normal memory cell array unit;
- a row redundancy address buffer unit for receiving a highest row address signal from the general address buffer, the test mode signal, and the row address counter signal and for generating a row redundancy address signal;
- row redundancy predecoder and decoder units for receiving the row address data signal, the test mode signal and the row redundancy address signal and for generating a signal to select redundancy word lines of the redundancy memory cell array unit;
- a column address buffer unit for receiving a column address signal from the general address buffer and for generating a column address data signal;
- column predecoder and decoder units for receiving the column address data signal and for generating a signal to select column lines of the normal memory cell array unit;
- a column redundancy address buffer unit for receiving a highest column address signal from the general address buffer and the test mode signal and for generating a column redundancy address signal;
- and
- column redundancy predecoder and decoder units for receiving the column address data signal, the test mode signal and the column redundancy address signal and for generating a signal to select redundancy column lines of the redundancy memory cell array unit.
12 more elements
The semiconductor memory device having a redundancy circuit, comprising:
- a normal memory cell array unit comprising N memory banks for storing a plurality of data;
- a redundancy memory cell array unit comprising N memory banks for recovering defective cells of the normal memory cell array unit;
- a test mode signal generating unit for generating a test mode signal indicating a test operation;
- a row address counter unit for receiving the test mode signal, a first signal enabled in a refresh mode and a second signal toggling once in a refresh mode and for generating a row address counter signal;
- a row counter reset unit for receiving the test mode signal, the second signal and a part of the row address counter signal and for generating a reset signal to reset the row address counter unit;
- a row counter reset initialization unit for receiving the test mode signal and for generating an initialization signal to initialize the row counter reset unit;
- a row address buffer unit for receiving the row address counter signal and a row address signal from an address source and for generating a row address data signal;
- N row predecoder and decoder units for receiving the row address data signal and for generating a signal to select word lines of the normal memory cell array unit;
- a row redundancy address buffer unit for receiving a highest row address signal from the address source, the test mode signal and the row address counter signal and for generating a row redundancy address signal;
- N row redundancy predecoder and decoder units for receiving the row address data signal, the test mode signal and the row redundancy address signal and for generating a signal to select redundancy word lines of the redundancy memory cell array unit;
- a column address buffer unit for receiving a column address signal from the address source and for generating a column address data signal;
- N column predecoder and decoder units for receiving the column address data signal and for generating a signal to select column lines of the normal memory cell array unit;
- a column redundancy address buffer unit for receiving a highest column address signal from the address source and the test mode signal and for generating a column redundancy address signal;
- N column redundancy predecoder and decoder units for receiving the column address data signal, the test mode signal and the column redundancy address signal and for generating a signal to select redundancy column lines of the redundancy memory cell array unit;
- a bank address buffer unit for receiving an address signal having address data of the memory banks;
- and
- a bank control unit for generating a signal to selectively control the operations of the N row predecoder and decoder units, the N row redundancy predecoder and decoder units, the N column predecoder and decoder units and N column redundancy predecoder and decoder units by using a decoding address signal received from the bank address buffer unit based on the test mode signal.
14 more elements
Dependencies are inferred from the claim text.