US 6,639,850 B2Granted

Semiconductor integrated circuit having latching means capable of scanning

AssigneeKabushiki Kaisha Toshiba

InventorRyo Fukuda

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Abstract

A plurality of first registers are connected in series, and shift stored data to respective adjacent registers in sequence. A plurality of second registers are connected in series, and shift stored data to respective adjacent registers in sequence. The plurality of first and second registers are connected in one-to-one correspondence to a plurality of input terminals or to a plurality of output terminals. A first scan input terminal is formed at one end of the plurality of first series-connected registers, and a first scan output terminal is formed at the other end. A second scan input terminal is formed at one end of the plurality of second series-connected registers, and a second scan output terminal is formed at the other end. An operation control circuit controls operations of the circuits and the plurality of first and second registers.

Claims16

Dependent claims

A semiconductor integrated circuit comprising:

circuits having a certain function;
a plurality of input terminals which receive input data to said circuits from the outside;
a plurality of output terminals which output data output from said circuits to the outside;
a plurality of first registers connected in series, said plurality of first registers shifting stored data to respective adjacent registers in sequence, and said plurality of first registers being connected in one-to-one correspondence to said plurality of input terminals or to said plurality of output terminals;
a plurality of second registers connected in series, said plurality of second registers shifting stored data to respective adjacent registers in sequence, and said plurality of second registers being connected in one-to-one correspondence to said plurality of input terminals or to said plurality of output terminals;
a first scan input terminal formed at one end of said plurality of first series-connected registers;
a first scan output terminal formed at the other end of said plurality of first series-connected registers, said first scan output terminal being arranged in an end portion;
a second scan input terminal formed at one end of said plurality of second series-connected registers, said second scan input terminal being arranged in the same end portion as said first scan output terminal;
a second scan output terminal formed at the other end of said plurality of second series-connected registers;
and
an operation control circuit which controls operations of said circuits and said plurality of first and second registers.

8 more elements

A semiconductor integrated circuit comprising:

circuits having a certain function;
a plurality of input terminals which receive input data to said circuits from the outside;
a plurality of output terminals which output data output from said circuits to the outside;
a plurality of first registers connected in series, said plurality of first registers shifting stored data to respective adjacent registers in sequence, and said plurality of first registers being connected in one-to-one correspondence to said plurality of input terminals and said plurality of output terminals;
a plurality of buffers connected in series, said plurality of buffers amplifying data;
a first scan input terminal formed at one end of said plurality of first series-connected registers;
a first scan output terminal formed at the other end of said plurality of first series-connected registers;
a second scan input terminal formed at one end of said plurality of series-connected buffers;
a second scan output terminal formed at the other end of said plurality of series-connected buffers;
and
an operation control circuit which controls operations of said circuits and said plurality of first registers.

8 more elements

A semiconductor integrated circuit comprising:

circuits having a certain function;
a plurality of input terminals which receive input data to said circuits from the outside;
a plurality of output terminals which output data output from said circuits to the outside;
a plurality of first registers connected in series, said plurality of first registers shifting stored data to respective adjacent registers in sequence, and said plurality of first registers being connected in one-to-one correspondence to said plurality of input terminals and said plurality of output terminals;
a plurality of first buffers connected in series, said plurality of first buffers amplifying data;
a first scan input terminal formed at one end of said plurality of first series-connected registers;
a first scan output terminal formed at the other end of said plurality of first series-connected registers;
a second scan input terminal formed at one end of said plurality of first series-connected buffers;
a second scan output terminal formed at the other end of said plurality of first series-connected buffers;
an operation control circuit which outputs a clock signal for controlling a data shift operation of said plurality of first registers;
and
a plurality of second buffers which delay the clock signal output from said operation control circuit and supply the delayed clock signal to said plurality of first registers.

9 more elements

Dependencies are inferred from the claim text.