Method and circuit configuration for a memory for reducing parasitic coupling capacitances
AssigneeInfineon Technologies AG
InventorWolfgang Nikutta
Life of this patent
Estimating the term…
Abstract
A method and a circuit configuration for a dynamic semiconductor memory are described in which, in order to reduce the parasitic coupling effects between two adjacent bit lines, in particular between a read line and a reference line, the adjacent line is put at a predetermined potential during the read operation. As a result, the read signal, which is very small in the worst-case scenario, is not adversely influenced by the coupling capacitance, since the inactive adjacent line acts as capacitive shielding. Advantageously, the read signals of the various active bit lines cannot mutually influence one another. A further refinement of the invention provides for the potential to be kept at the magnitude of the precharge state.
Claims14
A memory circuit configuration, comprising:
- word lines disposed in a column form;
- bit lines disposed in a row form;
- sense amplifiers;
- and
- a multiplicity of memory cells, each of said memory cells including a single transistor and a storage capacitor;
- said memory cells being connected to and activated by said word lines, said bit lines connecting said memory cells to said sense amplifiers, upon activating a respective word line of said word lines, at least one of said bit lines being a first bit line and being associated with a respective memory cell of said memory cells, electrically connecting said respective memory cell to a respective first sense amplifier of said sense amplifiers for reading-out a datum, a second sense amplifier of said sense amplifiers during the reading-out on said first bit line putting an adjacent one of said bit lines being a second bit line adjacent to said first bit line actively at a precharge potential;
- said second bit line being associated with said second sense amplifier of said sense amplifiers, said second amplifier being disposed in a different activation array at an opposite side of a field of bit lines with respect to said first sense amplifier;
- one side of each of said sense amplifiers being associated with a pair of said bit lines, a bit line of a second of said sense amplifiers being disposed between a pair of bit lines of first of said sense amplifiers.
A method for reading a datum from a memory cell of a memory array via a first bit line, the memory array having a plurality of bit lines being disposed next to one another, which comprises the steps of:
- providing the memory cell with a single transistor and a storage capacitor;
- activating a word line connected to the memory cell for connecting the first bit line associated with a first sense amplifier to the memory cell;
- putting at least one second bit line disposed next to the first bit line and being associated with at least a second sense amplifier different than the first sense amplifier at a defined voltage;
- connecting each sense amplifier to a pair of the bit lines and placing a bit line of the second sense amplifier between the pair of bit lines of the first sense amplifier;
- and
- reading-out and evaluating a voltage impressed on the first bit line.
Dependencies are inferred from the claim text.