Non-volatile memory architecture and integrated circuit comprising a corresponding memory
AssigneeSTMicroelectronics S.r.l.
InventorsRichard Fournel, Sigrid Thomas, Cyrille Dray
Life of this patent
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Abstract
A non-volatile memory architecture with a word-based organization includes one selection transistor per word. This selection transistor is used for the selection of the word by the source of the memory cells. In this way, the selection may be done directly by the ouput signals from the address decoders using low voltage. The switching of a high voltage to the gates and the drains of the memory cells is done independently of this selection. This enables the required number of high voltage switches to be reduced.
Claims36
A non-volatile memory comprising:
- an array of memory cells arranged in rows and columns, and organized in words, each word being defined by a plurality of memory cells in a same row, and each memory cell comprising a memory effect transistor including a control terminal, a first conducting terminal, and a second conducting terminal;
- bit lines connected to the first conducting terminals of said memory effect transistors;
- an address decoder for providing a row-selection signal and a column-selection signal for selecting a word;
- a plurality of control terminal lines connected to the control terminals of said memory effect transistors, each respective control terminal line being connected in common to the control terminals of said memory effect transistors of a same row;
- and
- a plurality of selection transistors connected to the second conducting terminals of said memory effect transistors, each selection transistor for selecting a respective word, and being controlled by the row-selection signal and the column-selection signal for selecting the respective word.
A non-volatile memory comprising:
- an array of memory cells arranged in rows and columns, and organized in words, each word being defined by a plurality of memory cells in a same row, and each memory cell comprising a memory effect transistor including a control terminal, a first conducting terminal, and a second conducting terminal;
- bit lines connected to the first conducting terminals of said memory effect transistors;
- an address decoder for providing a low-voltage row-selection signal and a low-voltage column-selection signal for selecting a word;
- a plurality of control terminal lines connected to the control terminals of said memory effect transistors and being grouped together in at least groups of two, each respective control terminal line being connected in common to the control terminals of said memory effect transistors of a same row;
- a bias circuit connected to said plurality of control terminal lines and comprising a plurality of high-voltage switching circuits providing a high voltage signal relative to the low-voltage row-selection signal and to the low-voltage column-selection signal, each group of control terminal lines being controlled by a respective high-voltage switching circuit;
- and
- a plurality of selection transistors connected to the second conducting terminals of said memory effect transistors, each selection transistor for selecting a respective word, and being controlled by the low-voltage row-selection signal and the low-voltage column-selection signal for selecting the respective word.
A method for operating a non-volatile memory comprising an array of memory cells arranged in rows and columns and organized in words, each memory cell comprising a memory effect transistor;
- a plurality of control terminal lines connected to control terminals of the memory effect transistors, each control terminal line being connected in common to control terminals of the memory effect transistors of a same row;
- bit lines connected to first conducting terminals of the memory effect transistors;
- a plurality of control terminal lines connected to the control terminals of the memory effect transistors;
- and a plurality of selection transistors connected to second conducting terminals of the memory effect transistors, each selection transistor for selecting a respective word, the method comprising:
- selecting a word in the array of memory cells by providing a low-voltage row-selection signal and a low-voltage column-selection signal to a corresponding selection transistor, and a high-voltage to the bit lines connected to the first conducting terminals of the memory effect transistors forming the selected word;
- and
- writing data to the selected word by providing a high-voltage to a control terminal line connected to the control terminals of the memory effect transistors forming the selected word.
A method according to claim 34, wherein the non-volatile memory further comprises a plurality of read circuits, each read circuit connected to a respective group of bit lines;
- and further comprising reading the selected word by precharging the respective group of bit lines for the selected word based upon receiving an activation command before a start of a read cycle or a start of a succession of read cycles;
- and providing data read from the selected word.
Dependencies are inferred from the claim text.