Memory architecture
AssigneeInfineon Technologies AG
InventorsJoerg Wohlfahrt, Norbert Rehm, Michael Jacob, Thomas Roehr
Life of this patent
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Abstract
An IC with memory cells arranged in groups is described. The memory cells, for example, are ferroelectric memory cells. The IC includes a variable voltage generator (VVG) for generating an output voltage having a different voltage level depending on a location of an addressed memory cell within the memory group is provided. By providing different voltage levels for reads and/or writes, signal loss caused by capacitances which is dependent on the location of the memory cell within the group can be avoided. This improves read and/or write operations in series memory architectures.
Claims28
An integrated circuit comprising:
- a plurality of memory cells coupled in series to form a memory group;
- a plateline coupled to a first end of the memory group;
- and
- a variable voltage generator (VVG) for generating an output voltage, the output voltage has a different output voltage level depending on a location of an addressed memory cell within the memory group, the output voltage provided at the plateline during memory access.
A method for operating an integrated circuit comprising:
- providing a plurality of memory cells interconnected by platelines, bitlines and wordlines;
- and
- during a read memory access to one of the memory cells, generating a read pulse on at least one of the platelines associated with the one memory cell accessed, the read pulse comprises a different voltage level depending on a location of the memory cell accessed.
Dependencies are inferred from the claim text.