Back to results
US 6,639,820 B1Granted
Memory buffer arrangement
AssigneeIntel Corporation
InventorsNarendra S. Khandekar, James M. Dodd
Life of this patent
Estimating the term…
Abstract
Memory modules, memory systems, and computing devices are described which include memory buffer devices that buffer signals of memory devices. In some embodiments, the memory buffer devices are positioned to reduce the circuit board footprint of the memory buffer devices.
Claims27
A memory module comprising
- a circuit board comprising at least one lead,
- a plurality of first memory devices attached to the circuit board,
- a first buffer device attached to the circuit board and coupled between the at least one lead and the plurality of first memory devices to buffer signaling therebetween, and
- a second buffer device stacked upon the first buffer device and coupled between the at least one lead and the plurality of first memory devices to buffer signaling therebetween.
1 more element
For use with a memory controller, a memory module comprising
- a circuit board,
- a plurality of memory devices coupled to the circuit board to store data,
- a first integrated circuit coupled to the circuit board to buffer signals between the memory controller and the plurality of memory devices, and
- a second integrated circuit to buffer signals between the memory controller and the plurality of memory devices, wherein
- at least a portion of the first integrated circuit lies between the second integrated circuit and the circuit board.
2 more elements
A memory subsystem, comprising
- a plurality of memory devices to store data,
- a memory controller to generate memory address signals in response to requests to read data from the plurality of memory devices,
- a first buffer device coupled between the memory controller and the plurality of memory devices to send data signals to the memory controller based upon data retrieved from the plurality of memory devices, and
- a second buffer device positioned over the first buffer device and coupled between the memory controller and the plurality of memory devices to address the plurality of memory devices based upon the memory address signals.
1 more element
A computing device, comprising
- a plurality of volatile memory devices to store data,
- a processor to generate requests to read data from the plurality of volatile memory devices,
- a memory controller to receive the requests of the processor and to generate address signals In response to the requests,
- a first buffer device comprising first leads coupled to the memory controller to receive the address signals of the memory controller and second leads coupled to the memory controller to provide the memory controller with data signals representative of data stored by a volatile memory device of the plurality of volatile memory devices, and
- a second buffer device comprising first leads coupled to the first leads of the first buffer device to receive the address signals from the memory controller via the first leads of the first buffer device and to respectively apply address signals to the volatile memory device of the plurality of volatile memory devices.
2 more elements
Dependencies are inferred from the claim text.