Liquid crystal display

A liquid crystal display having active matrix type liquid crystal display elements comprising switching elements connected to a plurality of scanning lines and a plurality of picture signal lines perpendicular to said scanning lines, said liquid crystal display including a scanning line driving circuit and a picture signal line driving circuit, said scanning line driving circuit applying a scanning pulse to said switching elements via said scanning lines and said picture signal line driving circuit applying a picture signal to said picture signal lines, at least one of said scanning line driving circuit and said picture signal line driving circuit comprising a digital circuit, said digital circuit comprising one stage of CMOS buffer or a plurality of CMOS buffers connected in multi stages, said CMOS buffer or each of said CMOS buffers including an N-type thin-film transistor and P-type thin-film transistor which are formed on the same substrate,

• wherein one transistor, which has a longer off-state time during operation of the circuit, of said N-type thin-film transistor and P-type thin-film transistor constituting said CMOS buffer, has a narrower gate width than that of the other transistor, and
• wherein said digital circuit comprises a plurality of CMOS buffers, said one transistor of each of said CMOS buffers having a gate length of L2, said other transistor of each of said CMOS buffers having a gate length of L1 (L2>L1), said one transistor of a downstream side one of said CMOS buffers having a gate width which is set to be greater than that of said one transistor of an upstream side one of said CMOS buffers, and said gate width of said other transistor of said downstream side one of said CMOS buffers being set to be greater than that of said other transistor of said upstream side one of said CMOS buffers.

A liquid crystal display having active matrix type liquid crystal display elements comprising switching elements connected to a plurality of scanning lines and a plurality of picture signal lines perpendicular to said scanning lines, said liquid crystal and a plurality of picture signal lines perpendicular to said scanning lines, said liquid crystal display including a scanning line driving circuit and a picture signal line driving circuit, said scanning line driving circuit applying a scanning pulse to said switching elements via said scanning lines and said picture signal line driving circuit applying a picture signal to said picture signal lines, at least one of said scanning line driving circuit and said picture signal line driving circuit comprising a digital circuit, said digital circuit comprising one stage of CMOS buffer or a plurality of CMOS buffers connected in multi stages, said CMOS buffer or each of said CMOS buffers including an N-type thin-film transistor and P-type thin-film transistor which are formed on the same substrate,

• wherein, one transistor, which has a longer off-state time during operation of the circuit, of said N-type thin-film transistor and P-type thin-film transistor constituting said CMOS buffer, has a longer gate length than that of the other transistor, and said one transistor has a narrower gate width than that of said other transistor,
• wherein said digital circuit comprises a plurality of CMOS buffers, said one transistor of a downstream side one of said CMOS buffers having a gate width which is set to be greater than that of said one transistor of an upstream side one of said CMOS buffers, and said gate width of said other transistor of said downstream side one of said CMOS buffers being set to be greater than that of said other transistor of said upstream side one of said CMOS buffers.

A liquid crystal display having active matrix type liquid crystal display elements comprising switching elements connected to a plurality of scanning lines and a plurality of picture signal lines perpendicular to said scanning lines, said liquid crystal display including a scanning line driving circuit and a picture signal line driving circuit, said scanning line driving circuit applying a scanning pulse to said switching elements via said scanning lines and said picture signal line driving circuit applying a picture signal to said picture signal lines, at least one of said scanning line driving circuit and said picture signal line driving circuit comprising a digital circuit, said digital circuit comprising one stage of CMOS buffer or a plurality of CMOS buffers connected in multi stages, said CMOS buffer or each of said CMOS buffers including an N-type thin-film transistor and P-type thin-film transistor which are formed on the same substrate,

• wherein one transistor, which has a longer off-state time during operation of the circuit, of said N-type thin-film transistor and P-type thin-film transistor constituting said CMOS buffer, has a narrower gate width than that of the other transistor, and
• wherein said digital circuit comprises a plurality of CMOS buffers, said one transistor of each of said CMOS buffers having the same gate length as that of said other transistor of a corresponding one of said CMOS buffers.