Asynchronous glitch-free clock multiplexer
AssigneeLattice Semiconductor Corporation
InventorsLouis De La Cruz, Chris Hume
Life of this patent
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Abstract
A clock multiplexer selects between two asynchronous clock signal inputs to produce a clock signal output such that the clock signal input corresponding to the clock signal output may be denoted as the current clock signal and the remaining clock signal input may be denoted as the selected clock signal. After detecting an edge of a specified type in the current clock signal, the clock multiplexer holds the clock signal output either high or low according to the specified type of clock edge being detected. After detecting an edge of the specified type in the selected clock signal, the clock signal output is released and the selected clock signal allowed to pass.
Claims17
A clock multiplexer system, comprising:
- a clock multiplexer operable to select between a first and a second clock signal input and to provide a clock signal output responsive to a selection signal, wherein the two clock signal inputs represent a current clock signal corresponding to the clock signal output and a remaining selected clock signal;
- a first edge detector operable to detect a clock edge of a specified type on the current clock signal responsive to the selection signal;
- a second edge detector operable to detect a clock edge of the specified type on the selected clock signal responsive to an indication from the first edge detector that the clock edge of the specified type on the current clock signal has been detected;
- and
- a controller configured to control the selection of the two clock signal inputs by the clock multiplexer.
A method of selecting between two clock signal inputs to produce an output clock signal, wherein the two clock signal inputs represent a current clock signal corresponding to the clock signal output and a remaining selected clock signal, comprising:
- (a) detecting a clock edge of a specified type in the current clock signal;
- and
- subsequent to act (a):
- (b) if the specified type of clock edge is a falling clock edge, holding the output clock signal low, and if specified type of clock edge is a rising clock edge, holding the output clock signal high;
- and
- (c) detecting an edge of the specified type in the selected clock signal;
- and
- subsequent to act (c):
- (d) releasing the hold on the output clock signal from act (b) and passing the selected clock signal as the clock output signal.
Dependencies are inferred from the claim text.