High linearity, high gain mixer circuit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsHiroshi Komurasaki, Hisayasu Sato, Kimio Ueda
Life of this patent
Estimating the term…
Abstract
A mixer circuit includes a first signal input terminal connected to the gate of a first MOSFET, and a second signal input terminal connected to the gate of a second MOSFET. The mixer circuit is configured such that a relationship (VG1−VGS2)<(VGS2−VT1) is established, where VG1 is a bias voltage applied to the gate of the first MOS transistor, VGS2 is a bias voltage applied to the gate of the second MOS transistor, and VT1 is a threshold voltage of the first MOS transistor, the bias voltages VG1 and VGS2 being each defined with respect to the source bias voltage of the second MOS transistor. This can implement high linearity mixer circuit even when operated at a low power supply voltage.
Claims17
A mixer circuit including a first mixer circuit comprising:
- a first impedance element that has a DC path and is connected to a first fixed bias point;
- a first MOS transistor having its drain connected to said first impedance element;
- a second MOS transistor having its drain connected to a source of said first MOS transistor;
- a second fixed bias point connected to a source of said second MOS transistor;
- a first signal input terminal that is connected to a gate of said first MOS transistor, the first signal input terminal being supplied with an RF signal;
- a second signal input terminal that is connected to a gate of said second MOS transistor, the second signal input terminal being supplied with a local signal;
- an output terminal connected to a connecting point of said first impedance element and said first MOS transistor;
- a first bias circuit for applying a bias voltage VG1 to the gate of said first MOS transistor, the bias voltage VG1 being defined with respect to said second fixed bias point;
- and
- a second bias circuit for applying a bias voltage VGS2 to the gate of said second MOS transistor, the bias voltage VGS2 being defined with respect to said second fixed bias point,
- wherein a relationship (VG1−VGS2)<(VGS2−VT1) is established, where VT1 is a threshold voltage of said first MOS transistor.
A mixer circuit including a first mixer circuit comprising:
- a first impedance element that has a DC path and is connected to a first fixed bias point;
- a first MOS transistor having its drain connected to said first impedance element;
- a second MOS transistor having its drain connected to a source of said first MOS transistor;
- a second fixed bias point connected to a source of said second MOS transistor;
- a first signal input terminal connected to a gate of said first MOS transistor;
- a second signal input terminal connected to a gate of said second MOS transistor;
- and
- an output terminal connected to a connecting point of said first impedance element and said first MOS transistor;
- wherein one of said first signal input terminal and said second signal input terminal is connected to a back gate of at least one of said first MOS transistor and said second MOS transistor.
Dependencies are inferred from the claim text.