Clock signal correction circuit and semiconductor device implementing the same
AssigneeFujitsu Quantum Devices Limited
InventorsMasaaki Ono, Masataka Kazuno, Narito Matsuno
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Abstract
A clock signal correction circuit which corrects duty cycle distortions of a clock signal in a simple and accurate way. A frequency divider divides the frequency of a given input clock signal by a natural number n, thereby producing a divided clock signal. The phase of this divided clock signal is identified by a phase detector. By adding an appropriate delay to the divided clock signal according to the identified signal phase, a delay unit produces a delayed divided clock signal. A logical operator creates an output clock signal by performing a logical operation on the original divided clock signal and the delayed divided clock signal.
Claims12
A clock signal correction circuit which corrects duty cycle distortions of an input clock signal, comprising:
- a frequency divider which divides the frequency of the input clock signal by a natural number n, thereby producing a divided clock signal;
- a phase detector which identifies the phase of the divided clock signal;
- a delay unit which produces a delayed divided clock signal by adding a delay to the divided clock signal according to the identified phase of the divided clock signal;
- and
- a logical operator which produces an output clock signal by performing a logical operation on the divided clock signal and delayed divided clock signal,
- wherein said phase detector includes a first delay element array having a plurality of delay elements which produce a first series of delayed signals by adding successively increasing delays to the divided clock signal, and an edge detector which identifies an edge position of the divided clock signal by examining the divided clock signal with reference to the first series of delayed signals produced by said first delay element array;
- wherein said delay unit includes a second delay element array having a plurality of delay elements which produces a second series of delayed signals by adding successively increasing delays to the divided clock signal, and a delayed signal selector which selects one of the second series of delayed signals that is associated with the edge position identified by said edge detector, and outputs the selected delayed signal as the delayed divided clock signal;
- and
- wherein said phase detector and said delay unit share a common delay element array as the first and second delay element arrays.
A semiconductor device on which a clock signal correction circuit is integrated to correct duty cycle distortions of an input clock signal, the clock signal correction circuit comprising:
- a frequency divider which divides the frequency of the input clock signal by a natural number n, thereby producing a divided clock signal;
- a phase detector which identifies the phase of the divided clock signal;
- a delay unit which produces a delayed divided clock signal by adding a delay to the divided clock signal according to the identified phase of the divided clock signal;
- and
- a logical operator which produces an output clock signal by performing a logical operation on the divided clock signal and delayed divided clock signal,
- wherein said phase detector includes a first delay element array having a plurality of delay elements which produce a first series of delayed signals by adding successively increasing delays to the divided clock signal, and an edge detector which identifies an edge position of the divided clock signal by examining the divided clock signal with reference to the first series of delayed signals produced by said first delay element array;
- wherein said delay unit includes a second delay element array having a plurality of delay elements which produces a second series of delayed signals by adding successively increasing delays to the divided clock signal, and a delayed signal selector which selects one of the second series of delayed signals that is associated with the edge position identified by said edge detector, and outputs the selected delayed signal as the delayed divided clock signal;
- and
- wherein said phase detector and said delay unit share a common delay element array as the first and second delay element arrays.
Dependencies are inferred from the claim text.