Reducing voltage variation in a phase locked loop
AssigneeSun Microsystems, Inc.
InventorsClaude R. Gauthier, Pradeep R. Trivedi, Dean Liu, Brian Amick
Life of this patent
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Abstract
A method for reducing voltage variation in the power supply system of a phase locked loop has been developed. The method includes powering up a phase locked loop and activating or inserting a shunting resistance across the power supply terminals. The shunting resistance is inserted in parallel with the phase locked loop, and is controllable such that the resistance can be selectively switched ‘on’ and/or ‘off.’
Claims16
A method for reducing voltage variation in a phase locked loop, comprising:
- supplying power to the phase locked loop;
- and
- connecting a resistor in parallel with the phase locked loop.
A method for reducing voltage variation in a phase locked loop, comprising:
- supplying power to the phase locked loop;
- and
- shunting a resistor in parallel with the phase locked loop.
An apparatus for decreasing clock jitter in a phase locked loop, comprising:
- a phase locked loop;
- a power supply system connected to phase locked loop;
- and
- a shunting resistor connected across power supply system in parallel with the phase locked loop.
An apparatus for reducing voltage variation in a phase locked loop, comprising:
- means for supplying power to the phase locked loop;
- and
- means for connecting resistor in parallel with the phase locked loop.
Dependencies are inferred from the claim text.