Method and apparatus for data sampling

A method for sampling input data, comprising:

• providing a base clock having a frequency that is greater than a normal frequency of the input data;
• detecting a level-turning point of the input data in response to the base clock;
• generating responsive to the base clock a plurality of source clocks having different phases shifted by one cycle of the base clock one by one;
• selecting one of the plural source clocks having a first level-turning point synchronized with the level-turning point of the input data and a second level-turning point generated right in a middle of a normal cycle of the input data;
• generating an average phase signal representing an average of phases of previous selected source clocks;
• selecting one of the average phase signal and a currently selected source clock as a sampling clock to be actually used for sampling;
• comparing a previous selected source clock and the currently selected source clock to detect a phase difference therebetween;
• sampling the input data in synchronization with the sampling clock;
• and
• prohibiting the sampling operation when the phase difference between the previous selected source clock and the currently selected source clock is larger than a predetermined threshold value.

A data sampling circuit, comprising:

• an edge detecting circuit which detects a level-turning point of input data;
• a sampling clock generating circuit which generates a sampling clock in response to the level-turning point of the input data, the sampling clock generating circuit including
• a source clock generating circuit which generates a plurality of source clocks, and
• a clock selecting circuit which selects one of the source clocks;
• a clock-phase storing circuit which generates an average phase signal representing an average of phases of previous selected source clocks,
• said sampling clock generating circuit selecting one of the average phase signal and a currently selected source clock as the sampling clock to be actually used for sampling;
• and
• a logic circuit which samples the input data in synchronization with the sampling clock.

A data sampling circuit, comprising:

• a PLL (Phase Locked Loop) circuit which generates a base clock having a frequency that is greater than a normal frequency of input data;
• an edge detecting circuit which detects a level-turning point of the input data in response to the base clock;
• a source clock generating circuit which generates, in response to the base clock, a plurality of source clocks having different phases shifted by one cycle of the base clock one by one;
• a clock selecting circuit which selects one of the plural source clocks having a first level-turning point synchronized with the level-turning point of the input data and a second level-turning point generated right in a middle of a normal cycle of the input data;
• a clock-phase storing circuit which generates an average phase signal representing an average phase of previous selected source clocks,
• said clock selecting circuit selecting one of the average phase signal and a currently selected source clock as a sampling clock to be actually used for sampling;
• and
• a logic circuit sampling the input data in synchronization with the sampling clock,
• said clock-phase storing circuit comparing a previous selected source clock and the currently selected source clock to detect a phase difference therebetween, and prohibiting the sampling operation when the phase difference between the previous selected source clock and the currently selected source clock is larger than a predetermined threshold value.