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US 6,639,436 B2Granted
Semiconductor integrated circuit with function to start and stop supply of clock signal
AssigneeFujitsu Limited
InventorsYoshikazu Yamada, Masami Kanasugi, Shoji Taniguchi, Koichi Kuroiwa
Life of this patent
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Abstract
A semiconductor integrated circuit includes a plurality of functional blocks, each of which starts and stops an operation thereof in response to assertion and negation, respectively, of a corresponding command signal, a clock generation circuit which generates a clock signal, a clock control circuit which starts supplying the clock signal to each of the functional blocks in response to the assertion of the corresponding command signal, and stops supplying the clock signal to each of the functional blocks in response to the negation of the corresponding command signal.
Claims9
A semiconductor integrated circuit, comprising:
- a plurality of functional blocks, each of which starts and stops an operation thereof in response to assertion and negation, respectively, of a corresponding command signal;
- a clock generation circuit which generates a clock signal;
- a clock control circuit which starts supplying the clock signal to each of said functional blocks in response to the assertion of the corresponding command signal, and stops supplying the clock signal to each of said functional blocks in response to the negation of the corresponding command signal;
- and
- a controller which controls the command signal with respect to each of said functional blocks,
- wherein at least one of said functional blocks includes a register that stores therein the corresponding command signal, said controller setting the command signal in said register to a state of assertion, said at least one of said functional blocks resetting the command signal in said register to a state of negation upon completion of an operation of said at least one of said functional blocks.
3 more elements
A method of controlling a clock, comprising the steps of:
- generating a clock signal that is to be supplied to a plurality of functional blocks, each of which starts and stops an operation thereof in response to assertion and negation, respectively, of a corresponding command signal;
- starting supplying the clock signal to each of said functional blocks in response to the assertion of the corresponding command signal;
- stopping supplying the clock signal to each of said functional blocks in response to the negation of the corresponding command signal;
- and
- delaying the command signal, wherein said step of starting supplying the clock signal starts supplying the clock signal in response to the assertion of the delayed command signal, and said step of stopping supplying the clock signal stops supplying the clock signal in response to the negation of the delayed command signal.
2 more elements
A method of controlling a clock, comprising the steps of:
- generating a clock signal that is to be supplied to a plurality of functional blocks, each of which starts and stops an operation thereof in response to assertion and negation, respectively, of a corresponding command signal;
- starting supplying the clock signal to each of said functional blocks in response to the assertion of the corresponding command signal;
- stopping supplying the clock signal to each of said functional blocks in response to the negation of the corresponding command signal;
- and
- delaying the command signal by a first delay length and delaying the command signal by a second delay length, wherein said step of starting supplying the clock signal starts supplying the clock signal in response to the assertion of the command signal delayed by the first delay length, and said step of stopping supplying the clock signal stops supplying the clock signal in response to the negation of the command signal delayed by the second delay length.
2 more elements
A method of controlling a clock, comprising the steps of:
- generating a clock signal that is to be supplied to a plurality of functional blocks, each of which starts and stops an operation thereof in response to assertion and negation, respectively, of a corresponding command signal;
- starting supplying the clock signal to each of said functional blocks in response to the assertion of the corresponding command signal;
- stopping supplying the clock signal to each of said functional blocks in response to the negation of the corresponding command signal;
- and
- delaying the command signal by a first delay length and delaying the command signal by a second delay length, wherein said step of starting supplying the clock signal and said step of stopping supplying the clock signal supply the clock signal having start and stop timings that are controlled in accordance with a state of the command signal delayed by the first delay length, and supply another one of the clock signal having start and stop timings that are controlled in accordance with a state of the command signal delayed by the second delay length.
2 more elements
Dependencies are inferred from the claim text.