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US 6,639,435 B2Granted
Adjustable frequency divider
AssigneeInfineon Technologies AG
InventorJosef Hölzle
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Abstract
The novel frequency divider has an adjustable divider ratio. Such circuits are subject to demands for ever higher clock frequencies. The circuit generates the output signal in a blockwise manner and converts it into a sequential signal in a parallel-serial converter on the output side and outputs it in a bitwise manner. As a result, the essential part of the frequency divider circuit can be operated with a slower frequency than the input frequency, which in turn enables higher input frequencies.
Claims7
A frequency divider, comprising:
- an input terminal for receiving an input signal with a first clock frequency and an output terminal for an output signal;
- a state register, encompassing n bits, for storing a register state from a multiplicity of register states;
- a decoder connected to said state register, said decoder assigning to the register states in each case an m-bit word, a plurality of second n-bit words, and state-dependent variables;
- a loading device connected to said state register and configured to write, depending on an adjustable divider ratio and the state-dependent variables, one of the n-bit words to said state register at a second clock frequency corresponding to the frequency of the input signal divided by m;
- and
- a parallel-serial converter connected to said loading device for reading in the m-bit words in parallel at the second clock frequency and outputting the m-bit words serially as the output signal.
3 more elements
Dependencies are inferred from the claim text.