Differential input comparator

A differential input comparator, comprising:

• a first input terminal and a second input terminal to receive a differential input signal;
• at least two input sensing devices that generate at least two currents in response to voltage levels on the first input terminal and the second input terminal, each input sensing device having at least one P-type transistor coupled to one of the input terminals and one N-type transistor coupled to the other input terminal, wherein the currents generated by the sensing devices are used to generate a non-differential single-bit digital output indicative of a difference in polarity between the first input terminal and the second input terminal;
• a voltage bias circuit;
• and
• a source-following transistor coupled in series with one of the P-type or N-type transistors, the source following transistor having a gate coupled to the voltage bias circuit.

A comparator means for digitizing a differential input signal, comprising:

• means for receiving the differential input signal;
• means for sensing the differential input signal using at least two sensing devices that include P-type and N-type transistors coupled in parallel;
• means for generating currents in the individual sensing devices;
• means for combining the currents to produce a digital output;
• and
• a source-following transistor coupled in series with one of the P-type or N-type transistors.

A differential comparator, comprising:

• a first input terminal and a second input terminal to receive a differential input signal;
• at least two input sensing devices that generate at least two currents in response to voltage levels on the first and second input terminals;
• the input sensing devices having at least one P-type transistor coupled to one of the input terminals and one N-type transistor coupled to the other input terminal, wherein the P-type and N-type transistors are coupled in parallel;
• wherein the current generated by the sensing device is used to generate a single-bit digital output indicative of a difference in polarity between the input terminals;
• and
• further including a source-following transistor coupled in series with one of the P-type or N-type transistors.

A differential input comparator, comprising:

• a pair of differential amplifiers each coupled to first and second input terminals and operable to generate current signals corresponding to a difference between inputs signals applied to the input terminals, at least one of the differential amplifiers having a pair of input sensing devices, the input sensing devices having N-type and P-type transistors with a first transistor of one type having a gate coupled to the first input terminal and a first transistor of the other type having a gate coupled to the second input terminal and a source coupled to a source of a second transistor of the one type, the input sensing devices having a source-follower transistor coupled in series with one of the P-type or N-type transistors;
• a current-addition-and-subtraction circuit coupled to the first and second differential amplifiers and operable to combine the current signals;
• and
• a current-to-voltage converter coupled to the current-addition-and-subtraction circuit and operable to convert the combined current signal into a digital voltage signal.

A differential input comparator, comprising:

• a first input terminal and a second input terminal to receive a differential input signal;
• at least two input sensing devices that generate at least two currents in response to voltage levels on the first input terminal and the second input terminal;
• and
• each input sensing device having at least one P-type transistor coupled to one of the input terminals and one N-type transistor coupled to the other input terminal;
• wherein the currents generated by the sensing devices are used to generate a single-bit digital output indicative of a difference in polarity between the first input terminal and the second input terminal;
• a voltage bias circuit;
• and
• a source-following transistor coupled in series with one of the P-type or N-type transistors, the source-following transistor having a gate coupled to the voltage bias circuit.