High speed latch comparators
AssigneeBroadcom Corporation
InventorsKlaas Bult, Rudy Van de Plassche, Jan Mulder
Life of this patent
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Abstract
In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.
Claims28
A latch circuit, comprising:
- a bistable pair of transistors having a first transistor connected between a reset switch and a first supply voltage, having a second transistor connected between said reset switch and said first supply voltage, and having a first port capable of receiving a first current signal and producing a first output voltage, and a second port capable of receiving a second current signal and producing a second output voltage;
- and
- a vertical latch connected between said first supply voltage and a second supply voltage, and connected to said first port, said vertical latch having a third transistor connected between said second supply voltage and said first port, and a fourth transistor connected to said first supply voltage but isolated from said second supply voltage.
A latch circuit, comprising:
- a bistable pair of transistors connected between a reset switch and a first supply voltage, and having a first port capable of receiving a first current signal and producing a first output voltage, and a second port capable of receiving a second current signal and producing a second output voltage;
- and
- a vertical latch connected between said first supply voltage and a second supply voltage, and connected to said first port;
- wherein said vertical latch comprises:
- a first MOSFET current mirror pair connected to said bistable pair of transistors;
- and
- a second MOSFET current mirror pair connected to said first MOSFET current mirror pair.
A latch circuit, comprising:
- a bistable pair of transistors connected between a reset switch and a first supply voltage, and having a first port capable of receiving a first current signal and producing a first output voltage, and a second port capable of receiving a second current signal and producing a second output voltage,
- said bistable pair of transistors further including a first MOSFET and a second MOSFET connected to said first MOSFET, wherein a gate terminal of said first MOSFET is connected to a drain terminal of said second MOSFET, a gate terminal of said second MOSFET is connected to a drain terminal of said first MOSFET, and source terminals of said first and said second MOSFETs are connected to said first supply voltage;
- and
- a vertical latch connected between said first supply voltage and a second supply voltage, and connected to said first port;
- wherein said vertical latch comprises:
- a third MOSFET connected to said first MOSFET;
- and
- a fourth MOSFET connected to said third MOSFET;
- wherein:
- the source terminal of said third MOSFET is connected to said first supply voltage;
- a drain terminal of said third MOSFET is connected to a gate terminal of said fourth MOSFET;
- a source terminal of said fourth MOSFET is connected to said second supply voltage;
- and
- a drain terminal of said fourth MOSFET is connected to a gate terminal of said third MOSFET, said gate terminal of said first MOSFET, and said drain terminal of said second MOSFET.
A comparator, comprising:
- an input stage capable of receiving an analog signal;
- a latch circuit connected to said input stage, wherein said latch circuit has a bistable pair of transistors and a vertical latch, said vertical latch having a first transistor connected between a first supply voltage and a first port of said bistable pair, and a second transistor connected to a second supply voltage but isolated from said first supply voltage;
- and
- an output stage connected to said latch circuit, wherein said output stage is capable of retaining an output of said latch circuit.
In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a method for decreasing the time in which a latch circuit port receiving a current signal greater than a bias current reaches a steady state voltage, comprising the steps of:
- (1) amplifying, with the third transistor, the current signal greater than the bias current while maintaining a current signal less than the bias current received at a second latch circuit port;
- and
- (2) applying said amplified current signal to the latch circuit port receiving the current signal greater than the bias current.
In a latch circuit having a bistable pair and a vertical latch, wherein the bistable pair has a first MOSFET and a second MOSFET configured so that the drain terminal of the first MOSFET is connected to the gate terminal of the second MOSFET at a first port, the drain terminal of the second MOSFET is connected to the gate terminal of the first MOSFET at a second port, and the source terminals of the first and second MOSFETs are connected together, and wherein the vertical latch has a third MOSFET and a fourth MOSFET configured so that the gate terminal of the third MOSFET is connected to the gate terminal of the second MOSFET and the drain terminal of the fourth MOSFET, the source terminal of the third MOSFET is connected to a first supply voltage, the source terminal of the fourth MOSFET is connected to a second supply voltage, and the gate terminal of the fourth MOSFET is connected to the drain terminal of the third MOSFET, a method for reducing the power consumed by the latch circuit, comprising the steps of:
- (1) resetting the bistable pair and the vertical latch;
- and
- (2) holding the fourth MOSFET OFF during said resetting.
Dependencies are inferred from the claim text.