Method for clock control of half-rail differential logic
AssigneeSun Microsystems, Inc.
InventorSwee Yew Choe
Life of this patent
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Abstract
Clocked half-rail differential logic circuits are activated by a delayed clock. According to the invention, when clocked half-rail differential logic circuits of the invention are cascaded together, a delayed clock is provided for each clocked half-rail differential logic circuit and each delayed clock is timed to at least the delay of the previous clocked half-rail differential logic circuit. Consequently, according to the invention, a delay time is introduced to ensure each clocked half-rail differential logic circuit of the invention is switched or “fired” only after it has received an input from the previous clocked half-rail differential logic circuit stage. According to the invention, this is achieved without the use of complicated control circuitry.
Claims4
A method for creating a cascaded chain synchronous clocked half-rail differential logic circuits said method comprising:
- providing a first synchronous clocked half-rail differential logic circuit, said first clocked half-rail differential logic circuit comprising:
- a first synchronous clocked half-rail differential logic circuit clock input terminal;
- at least one first synchronous clocked half-rail differential logic circuit data input terminal;
- and
- at least one first synchronous clocked half-rail differential logic circuit data output terminal;
- providing a second synchronous clocked half-rail differential logic circuit, said second synchronous clocked half-rail differential logic circuit comprising:
- a second synchronous clocked half-rail differential logic circuit clock input terminal;
- at least one second synchronous clocked half-rail differential logic circuit data input terminal;
- and
- at least one second synchronous clocked half-rail differential logic circuit data output terminal;
- coupling a first clock signal to said first synchronous clocked half-rail differential logic circuit clock input terminal;
- coupling a second clock signal to said second synchronous clocked half-rail differential logic circuit clock input terminal;
- coupling said at least one first synchronous clocked half-rail differential logic circuit data output terminal to said at least one second synchronous clocked half-rail differential logic circuit data input terminal;
- and
- delaying said second clock signal with respect to said first clock signal by a predetermined delay time.
Dependencies are inferred from the claim text.