Method and system for dynamically clocking digital systems based on power usage

A digital circuit of run in conjunction with a system clock signal, the digital circuit comprising:

• a digital logic circuitry regulated by a clock signal and powered by a system current;
• a clocking circuitry, communicatively coupled to the digital logic circuitry and the system clock signal, for supplying the clock signal to the digital logic circuitry, the clocking circuitry comprising:
• a power supply monitor circuitry, communicatively coupled to the power supply, providing a signal indicative of current or power consumed by the system;
• a clock regulation circuitry, communicatively coupled to the power supply circuitry, that outputs the clock signal to the digital logic circuitry in response to the signal indicative of current or power consumed by the system;
• the clock signal comprising the system clock signal when the signal indicative of current or power consumed by the system is in a first state;
• the clock signal comprising a modified clock signal when the signal indicative of current or power consumed by the system is in a second state;
• and
• a modal circuitry having an output,
• wherein the clock regulation circuitry alters the clock signal in response to a logical combination of (i) the signal indicative of current or power consumed by the system and (ii) the output of the modal circuitry.

A digital circuit run in conjunction with a system clock signal, the digital circuit comprising:

• a digital logic circuitry regulated by a clock signal and powered by a system current;
• a clocking circuitry, communicatively coupled to the digital logic circuitry and the system clock signal, for supplying the clock signal to the digital logic circuitry, the clocking circuitry comprising:
• a power supply monitor circuitry, communicatively coupled to the power supply, providing a signal indicative of current or power consumed by the system;
• a clock regulation circuitry, communicatively coupled to the power supply circuitry, that outputs the clock signal to the digital logic circuitry in response to the signal indicative of current or power consumed by the system;
• the clock signal comprising the system clock signal when the signal indicative of current or power consumed by the system is in a first state comprising a predetermined level of said system current or power consumed by the system;
• the clock signal comprising a modified clock signal when the signal indicative of current or power consumed by the system is in a second state,
• wherein the predetermined level of system current or power consumed by the system is dynamically adaptable to vary the triggering condition of the modified clock signal in respect of the second state.

A digital system powered by a system current, the digital system having a system clock signal, the system comprising:

• a first logic circuitry clocked by a first clock signal;
• a second logic circuitry clocked by a second clock signal;
• the first and second logic circuitries powered by the system current;
• an adaptive clocking circuit, communicatively coupled to the first logic circuitry, the system current, and to the system clock, the adaptive clocking circuit supplying the first clock signal;
• the first clock signal being the system clock signal when the current consumed by the system is below a predetermined threshold;
• the first clock signal being another clock signal when the current consumed by the system is above the predetermined threshold;
• and
• the adaptive clocking circuit being constructed and arranged to (i) vary said another clock signal and level of system current consumed by the first logic circuitry, independently of clock rate and system current consumption of the second logic circuitry, when the current consumed by the system is above the predetermined threshold, and (ii) dynamically speed up or slow down or inhibit the first logic circuitry, in relation to the second logic circuitry, to responsively adjust system current consumption of the first and second logic circuitries so that current consumed by the system does not breach a current consumption budget of the system.

A method of altering a clock signal to a digital circuitry in a system based upon a current supplied to the system, the system running on a system clock, the method comprising:

• monitoring the current against a first predetermined current level;
• selectively clocking the digital circuitry based on the current, the step of selectively clocking comprising:
• generating a first clock if the step of monitoring indicates that the current is below the first predetermined level;
• generating a second clock if the step of monitoring indicates that the current is above the first predetermined level;
• and
• continuously varying the second clock in accordance with level of current consumed by the digital circuitry in relation to the current supplied to the system when the current supplied to the system is above the first predetermined level, and dynamically speeding up or slowing down the digital circuitry or inhibiting clock rate so that the digital circuitry runs at a clock rate that does not breach a total current consumption budget of the system.