Combined dynamic logic gate and level shifter and method employing same

A level shifting logic circuit, comprising:

• a pair of logic gates each having an output and configured such that only one output of said pair is applied at a time to a respective one of a pair of output switching circuits coupled to receive said outputs of said logic gates;
• and
• a pair of inputs, which transition in a first voltage range, to control said logic gates to produce a third output which transitions in a second voltage range, in response to the switching of said output switching circuits;
• wherein said first and second logic gates are OR logic gate circuits, and said third output provides an OR logic function output.

A level shifting logic circuit, comprising:

• a pair of logic gates each having an output and configured such that only one output of said pair is applied at a time to a respective one of a pair of output switching circuits coupled to receive said outputs of said logic gates;
• and
• a pair of inputs, which transition in a first voltage range, to control said logic gates to produce a third output which transitions in a second voltage range, in response to the switching of said output switching circuits
• wherein
• said pair of output switching circuits include first and second series connected driving transistors, a source of said first driving transistor being coupled to a reference voltage source which defines one endpoint of said second voltage range, and a drain of said second transistor being coupled to another reference voltage source which defines another endpoint of said voltage range,
• said first and second driving transistors are not turned on at the same time, and,
• each of said pair of logic gates are configured to apply a respective one of said output signals only when said third output signal has a state opposite to a state of a respective enabling signal coupled to a respective one of said first and second logic gates.

A level shifting logic circuit, comprising:

• a pair of logic gates each having an output and configured such that only one output of said pair is applied at a time to a respective one of a pair of output switching circuits coupled to receive said outputs of said logic gates;
• a pair of inputs, which transition in a first voltage range, to control said logic gates to produce a third output which transitions in a second voltage range, in response to the switching of said output switching circuits;
• and
• a first and a second inverters, each having an input coupled to said third output signal, said first inverter having an output coupled as an enabling control signal to a first of said pair of logic gates, and said second inverter having an output coupled as an enabling control signal to a second of said pair of logic gates.

A level shifting logic circuit, comprising:

• a pair of logic gates each having an output and configured such that only one output of said pair is applied at a time to a respective one of a pair of output switching circuits coupled to receive said outputs of said logic gates;
• and
• a pair of inputs, which transition in a first voltage range, to control said logic gates to produce a third output which transitions in a second voltage range, in response to the switching of said output switching circuits;
• wherein said first and second logic gates are NAND logic gate circuits and said third output provides an AND logic function output.

A level shifting logic circuit, comprising:

• a first logic circuit responsive to at least one applied logic signal for producing a first output signal which transitions within a first voltage range;
• a second logic circuit responsive to said at least one applied logic signal for producing a second output signal which transitions within said first voltage range;
• a third logic circuit responsive to first and second control signals for providing at an output a third output signal which transitions within a second voltage range different from said first voltage range;
• a first switching circuit for selectively applying said first output signal as said first control signal to said third logic circuit;
• and
• a second switching circuit for selectively applying said second output signal as said second control signal to said third logic circuit;
• said first and second switching circuits operating such that said third logic circuit does not receive said first and second control signals simultaneously.

A memory device, comprising:

• circuitry for storing data;
• and
• at least one level shifting logic circuit associated with said circuitry, said level shifting logic circuit comprising:
• a first logic circuit responsive to at least one applied logic signal for producing a first output signal which transitions within a first voltage range;
• a second logic circuit responsive to said at least one applied logic signal for producing a second output signal which transitions within said first voltage range;
• a third logic circuit responsive to first and second control signals for providing at an output a third output signal which transitions within a second voltage range different from said first voltage range;
• a first switching circuit for selectively applying said first output signal as said first control signal to said third logic circuit;
• and
• a second switching circuit for selectively applying said second output signal as said second control signal to said third logic circuit;
• said first and second switching circuits operating such that said third logic circuit does not receive said first and second control signals simultaneously.

A processor system, comprising:

• a processor;
• at least one memory device coupled to said processor, at least one of said memory device and said processor including at least one level shifting logic circuit comprising:
• a first logic circuit responsive to at least one applied logic signal for producing a first output signal which transitions within a first voltage range;
• a second logic circuit responsive to said at least one applied logic signal for producing a second output signal which transitions within said first voltage range;
• a third logic circuit responsive to first and second control signals for providing at an output a third output signal which transitions within a second voltage range different from said first voltage range;
• a first switching circuit for selectively applying said first output signal as said first control signal to said third logic circuit;
• and
• a second switching circuit for selectively applying said second output signal as said second control signal to said third logic circuit;
• said first and second switching circuits operating such that said third logic circuit does not receive said first and second control signals simultaneously.

A method of operating a logic circuit, comprising:

• providing first and second logic output signals transitioning within a first voltage range in response to at least one input logic signal which transitions within said first voltage range;
• providing at a logic circuit a third logic output signal which transitions within a second voltage range which differs from said first voltage range in response to first and second control signals applied as inputs to said logic circuit;
• and
• selectively applying said first and second logic output signals as said first and second control signals to said logic circuit in a manner which prevents simultaneous application of said first and second control signals to said logic circuit.

A method of logic circuit operation with inherent voltage level shifting, comprising:

• providing a pair of inputs transitioning within a first voltage range to a first logic gate;
• providing said pair of inputs to a second logic gate;
• selectively coupling an output of said first logic gate to a gate of a first large output transistor using a first enabling circuit;
• selectively coupling an output of said second logic gate to a gate of a second large output transistor using a second enabling circuit;
• generating a third output signal that transitions within a second voltage range by connecting a first source/drain of each of said first and second large output transistors to an output terminal and coupling a second source/drain of each of said first and second large output transistors to first and second respective reference voltage sources;
• inverting said third output signal to generate an input to said first and second enabling circuits;
• wherein for a low-to-high state change of said third output signal, configuring said first enabling circuit to couple the output of said first logic gate to said gate of said first large output transistor and configuring the second enabling circuit to de-couple the output of said second logic gate from said gate of said second large output transistor;
• and
• wherein for a high-to-low state change of said third output signal, configuring said first enabling circuit to de-couple the output of said first logic gate from said gate of said first large output transistor and configuring the second enabling circuit to couple the output of said second logic gate to said gate of said second large output transistor.