Flip chip package module and method of forming the same
AssigneeVIA Technologies, Inc.
InventorRay Chien
Life of this patent
Estimating the term…
Abstract
A flip-chip package module consists of a semiconductor chip, a heat sink plate, a dielectric layer and a metal interconnect layer. The semiconductor chip has a positive side with a plurality of die pads located thereon and a back side for mounting onto the heat sink plate. The dielectric layer is formed by depositing on the surface of the inner heat sink plate and encases the semiconductor chip therein. The metal interconnect layer is formed on the surface of the dielectric layer and includes a plurality of metal conductive wires. Each of the metal conductive wires connects to one of the die pads of the semiconductor chip through a via.
Claims24
A flip chip package module, comprising:
- a semiconductor chip having a first side with circuits and a plurality of die pads located thereon and a second side;
- a heat sink plate held said semiconductor chip by bonding onto said second side;
- a dielectric layer being deposited on the inner surface of said heat sink plate and encasing said semiconductor chip therein;
- and
- a metal interconnect layer located on the surface of said dielectric layer including a plurality of metal conductive wires, each of said metal conductive wires being connected to one of said die pads of said semiconductor chip through a via.
A method of forming a flip chip package module, comprising:
- providing a heat sink plate;
- bonding a second side of at least one semiconductor chip onto said heat sink plate, said semiconductor chip having a first side which has circuits and a plurality of die pads located thereon;
- depositing a dielectric layer on the inner surface of said heat sink plate and encasing said semiconductor chip therein;
- forming a plurality of via holes on the surface of said dielectric layer, each of said via holes touches one of said die pads on said first side of said semiconductor chip;
- forming a metal interconnect layer on the surface of said dielectric layer and during the same processing filling said via holes to form a plurality of vias;
- and
- forming a plurality of conductive wires and a plurality of pads on the surface of said metal interconnect layer through photo lithographic and etching processes.
Dependencies are inferred from the claim text.