Pin arrangement for high frequency integrated circuit
AssigneeHitachi, Ltd.
InventorsKumiko Takikawa, Satoshi Tanaka, Takashi Hashimoto, Yoshiyuki Okabe
Life of this patent
Estimating the term…
Loading patent…
AssigneeHitachi, Ltd.
InventorsKumiko Takikawa, Satoshi Tanaka, Takashi Hashimoto, Yoshiyuki Okabe
Estimating the term…
A pin layout which prevents degradation of a frequency characteristic of a low noise amplifier and a receiving mixer included in a semiconductor integrated circuit for dual-band transmission/reception wherein the circuit of the low noise amplifier is provided at a position where the distance from the end of a pin outside the package of the low noise amplifier to the pad is the shortest; ground pins of two low noise amplifiers and the high frequency signal pins are arranged respectively so as not to be adjacent to each other; the power source and ground pin of the low noise amplifier, and the power source and ground pin of the bias circuit are respectively separated; and high frequency signal wires do not intersect each other.
A semiconductor integrated circuit comprising a first amplifier for a first frequency band and a second amplifier for a second frequency band into which reception signals are to be inputted, the second frequency band being different from the first frequency band, and a receiving mixer for the first frequency band and a receiving mixer for the second frequency band into which outputs from said first amplifier and from said second amplifier are to be respectively inputted, on one chip,
Dependencies are inferred from the claim text.