Semiconductor integrated circuit having an integrated resistance region
AssigneeFujitsu Quantum Devices Limited
InventorJun Wada
Life of this patent
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Abstract
A semiconductor integrated circuit device comprises an active device and a resistance element formed monolithically on a common substrate wherein the resistance element includes a dummy pattern having a layered structure identical with a layered structure of the active device, and first and second electrodes are provided inside a mesa structure provided for the resistance element with a separation from a sidewall of the mesa structure, the first and second electrodes being formed in correspondence to openings formed in the dummy pattern.
Claims12
A semiconductor integrated circuit device, comprising:
- a substrate carrying thereon an epitaxial layer;
- a resistance element formed on a first region of said epitaxial layer;
- and
- an active device formed on a second region of said epitaxial layer,
- said first and second regions comprising first and second mesa regions respectively, said first and second regions being formed as a part of said epitaxial layer,
- said first region including at least a first metal electrode defined by first and second, mutually opposing sidewalls and a second metal electrode defined by third and fourth, mutually opposing sidewalls,
- each of said first and second sidewalls of said first electrode is offset away from a hypothetical extension of said sidewall of said first mesa region in an inward direction of said first mesa region,
- said fourth sidewall of said second electrode being in a flush relationship with said sidewall of said first mesa region.
A semiconductor integrated circuit device, comprising:
- a substrate carrying thereon an epitaxial layer;
- a resistance element formed on a first region of said epitaxial layer;
- an active device formed on a second region of said epitaxial layer, said first and second regions comprising first and second mesa regions respectively;
- a dummy pattern provided over said first mesa region such that said dummy pattern includes therein one or more openings which are located away from a mesa sidewall defining said first mesa region;
- a first electrode provided on said epitaxial layer in said opening;
- and
- a second electrode provided on said epitaxial layer outside of said dummy pattern.
A semiconductor integrated circuit device, comprising:
- a substrate carrying thereon an epitaxial layer;
- a resistance element formed on a first region of said epitaxial layer;
- an active device formed on a second region of said epitaxial layer, said first and second regions comprising first and second mesa regions respectively;
- a dummy pattern provided over said first mesa region such that said dummy pattern extends across a lateral boundary of said first mesa region at one or more locations;
- a first electrode provided on said first mesa region at a first side of said dummy pattern;
- and
- a second electrode provided on said first mesa region at a second, opposite side of said dummy pattern,
- said dummy pattern forming a closed ring-shaped pattern.
Dependencies are inferred from the claim text.