US 6,639,269 B1Granted

Electrically programmable memory cell configuration and method for fabricating it

AssigneeInfineon Technologies AG

InventorsFranz Hofmann, Josef Willer

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Abstract

A memory cell contains a planar transistor whose channel region is disposed at a bottom of a depression in a substrate. A floating gate electrode of the transistor adjoins the bottom of the depression, the bottom being provided with a first dielectric disposed on sidewalls of the depression. Since the floating gate electrode has a larger area than the channel region, a capacitance formed by a control gate electrode applied on the floating gate electrode and the floating gate electrode is greater than a capacitance formed by the floating gate electrode and the channel region. Two source/drain regions of the transistor likewise adjoin the sidewalls of the depression. An insulation, which is thicker than the first dielectric, isolates the floating gate electrode from the source/drain regions, so that the source/drain regions do not contribute to the coupling ratio.

Claims17

Dependent claims

An electrically programmable memory cell configuration, comprising:

a substrate having a surface and depressions each with a bottom and mutually opposite sidewalls formed therein;
a plurality of memory cells having planar transistors, each of said memory cells having a planar transistor disposed in said substrate, said planar transistor having:
two source/drain regions adjoining two of said sidewalls of said depression and extending from said surface of said substrate to said bottom of said depression;
a channel region disposed in said substrate in at least part of said bottom of said depression;
a first dielectric layer disposed on said bottom of said depression in a region of said channel region, said dielectric layer having a thickness allowing tunneling of electrons during programming, said channel region having a cross section being parallel to said surface of said substrate and intersects said two source/drain regions;
a floating gate electrode adjoining said first dielectric and partially disposed on at least two of said mutually opposite sidewalls of said depression and said depression being constricted but not filled by said floating gate electrode;
a second dielectric layer;
a control gate electrode disposed above said floating gate electrode and insulated from said floating gate electrode by said second dielectric;
and
an insulation spacer disposed on two of said sidewalls of said depression and extending from said surface of said substrate to said bottom of said depression for preventing a capacitance between said two source/drain regions and said floating gate electrode, said insulation spacer having a thickness eliminating tunneling during programming, said first dielectric layer extending from said insulation spacer of at least one of said sidewalls to the other of said sidewalls on said bottom of said depression, and parts of said floating gate electrode disposed on said two of said sidewalls of said depression adjoining said insulation spacer.

7 more elements

A method for fabricating an electrically programmable memory cell configuration, which comprises the steps of:

providing a substrate;
producing a depression having a bottom and sidewalls in the substrate;
applying a first dielectric disposed at least partially at the bottom of the depression, the first dielectric dimensioned with a thickness allowing tunneling during programming;
producing a channel region of a planar transistor of a memory cell in the substrate, the channel region adjoining the first dielectric;
forming two source/drain regions of the planar transistor by implantation of a surface of the substrate such that the two source/drain regions adjoin two mutually opposite sidewalls of the depression and extend from the surface of the substrate to the bottom of the depression and that a cross section through the channel region being parallel to the surface of the substrate, intersects the two source/drain regions;
providing an insulation spacer extending along the sidewalls of the depression from the surface of the substrate to the bottom of the depression to the two mutually opposite sidewalls of the depression;
providing the first dielectric layer extending from the insulation spacer of at least one of the sidewalls to the other of the sidewalls on the bottom of the depression;
applying a conductive layer to the depression resulting in the depression being constricted, but not filled, by the conductive layer;
patterning the conductive layer thus forming a floating gate electrode of the planar transistor, the floating gate electrode adjoining the first dielectric and the insulation spacer, the insulation spacer preventing a formation of a capacitance between the floating gate electrode and the two source/drain regions, and the insulation spacer dimensioned with a thickness eliminating tunneling during programming;
forming a second dielectric above the floating gate electrode;
and
forming a control gate electrode above the second dielectric.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/648,952Filed 25 Aug 2000 · continuation
Priority: DE 198 08 52727 Feb 1998
Granted: 28 Oct 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10B 41/40
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the peripheral circuit region
H10B 41/49
Simultaneous manufacture of periphery and memory cells: comprising different types of peripheral transistor
H10D 30/0411
Of FETs having insulated gates [IGFET]: of FETs having floating gates
H10D 30/683
Having only two programming levels: programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling