Method and structure for surface state passivation to improve yield and reliability of integrated circuit structures
AssigneeInternational Business Machines Corporation
InventorStephen K. Loh
Life of this patent
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Abstract
A method for passivating surface states in an integrated circuit structure having a gate conductor with a gate dielectric layer. The method comprises the step of fabricating a solid state source of fluorine in close proximity to the gate dielectric layer. In addition, an integrated circuit structure is provided. The structure comprises a substrate having a gate dielectric layer on the substrate and a gate conductor on the substrate above the gate dielectric layer. The gate conductor further comprises an edge and a solid state source of fluorine in close proximity to the gate dielectric layer.
Claims14
An integrated circuit structure comprising:
- a substrate having a gate dielectric layer on a surface thereof, at least a portion of the substrate being doped;
- a gate conductor on said substrate above a portion of said gate dielectric layer,
- a source and a drain implanted in said substrate extending at least partially under said gate conductor and isolated therefrom by said gate dielectric layer, forming source and drain overlap regions respectively;
- a solid state source of fluorine in close proximity to said overlap regions;
- and at least one collar formed in at least deep trench capacitor formed in said substrate adjacent to said gate conductor, said deep trench capacitor having a polysilicon contact;
- wherein said collar defining a region isolating said trench capacitor from said doped substrate region, said collar comprising a material selected from the group consisting of fluorinated silicon oxide and fluorine implanted silicon oxide.
Dependencies are inferred from the claim text.