US 6,639,260 B2Granted

Semiconductor device having a vertical semiconductor element

AssigneeDenso Corporation

InventorsTakashi Suzuki, Tsutomu Uesugi, Norihito Tokura

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Abstract

A vertical type MOS field effect transistor has a super junction structure between a source electrode and an N+-type drain region. The super junction structure is constituted by a plurality of P-type single crystal silicon regions and a plurality of N-type single crystal silicon regions. Each of the plurality of P-type single crystal silicon regions and each of the plurality of N-type single crystal silicon regions are arrayed alternately. The super junction has two parts, that is, a cell forming region where a MOS structure is disposed and a peripheral region located at a periphery of the cell forming region. The source electrode contacts one of the P-type single crystal silicon regions in the peripheral region while disposed away from an end portion of the peripheral region that is located at an outermost in the peripheral region.

Claims24

Dependent claims

A semiconductor device having a vertical type semiconductor element comprising:

a semiconductor substrate of a first conductive type;
a super junction structure formed on said semiconductor substrate, and having a structure in which a first semiconductor region of the first conductive type and a second semiconductor region of a second conductive type are arrayed alternately to constitute an element forming region for said vertical type semiconductor element and to constitute a peripheral region which is disposed at a periphery of said element forming region to laterally surround said element forming region, said peripheral region including an outer end portion of said super junction structure;
and
an electrode portion formed over said element forming region of said super junction structure and electrically connected to said vertical type semiconductor element, wherein:
said semiconductor substrate is electrically connected to said first semiconductor region, and
said electrode portion has a pattern an edge of which is located away from said outer end portion of said super junction structure, said electrode portion being electrically connected to said second semiconductor region disposed in said peripheral region.

3 more elements

A semiconductor device having a vertical type semiconductor element comprising:

a semiconductor substrate;
a cell region disposed on said semiconductor substrate, said cell region having a first super junction structure in which a first semiconductor region of a first conductive type and a second semiconductor region of a second conductive type are alternately aligned:
a peripheral region disposed on said semiconductor substrate to surround said cell region, said peripheral region having a second super junction structure in which a third semiconductor region of the first conductive type and a fourth semiconductor region of the second conductive type and a third semiconductor region of the first conductive type and a fourth semiconductor region of the second conductive type are alternately aligned;
a first electrode disposed over said cell region to electrically connect to said second semiconductor region, said first electrode having a pattern to be electrically connected to said fourth semiconductor region and to render an edge thereof far from an outer end portion of said peripheral region;
and
a second electrode electrically connected to said first semiconductor region.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/015,917Filed 17 Dec 2001
Priority: JP 2000-38344018 Dec 2000
Published: US 2002/0074596 A120 Jun 2002
Granted: 28 Oct 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10D 30/665
Vertical dmos [vdmos] fets: having edge termination structures
H10D 30/668
Vertical dmos [vdmos] fets: having trench gate electrodes, e.g. UMOS transistors
H10D 62/051
Manufacture or treatment: forming charge compensation regions, e.g. superjunctions
H10D 62/111
Reduced surface field [RESURF] PN junction structures: multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures