DRAM cell constructions

A DRAM cell, comprising:

• a capacitor;
• an insulative material over a portion of the capacitor;
• an amorphous silicon layer over the insulative material;
• and
• a transistor structure over the capacitor, the transistor structure comprising a gate over the insulative material and a source/drain region proximate the gate, the source/drain region being electrically connected with the DRAM capacitor through the amorphous silicon layer.

A DRAM cell, comprising:

• a capacitor comprising a storage node, a cell plate, and a dielectric material between the storage node and cell plate;
• a transistor structure over the capacitor and in electrical connection with the capacitor;
• and
• an electrically conductive path beside the storage node and extending through the dielectric material to the cell plate, the electrically conductive path providing power to the cell plate.

A semiconductor structure, comprising:

• a cell plate layer;
• a dielectric material oven the cell plate layer;
• a conductive storage node mass over the dielectric material;
• the conductive storage node mass, dielectric material and cell plate layer together defining a capacitor structure;
• a first substrate being defined to encompass the capacitor structure;
• a monocrystalline silicon substrate bonded to the first substrate and over the conductive storage node mass;
• a transistor gate on the monocrystalline silicon substrate and operatively connected with the capacitor structure to define a DRAM cell;
• a silicon-containing layer over the first capacitor structure;
• and
• wherein the monocrystalline silicon substrate is bonded on the silicon-containing layer.

A semiconductor structure, comprising:

• a cell plate layer;
• a dielectric material over the cell plate layer;
• a conductive storage node mass over the dielectric material;
• the conductive storage node mass, dielectric material and cell plate layer together defining a capacitor structure;
• a first substrate being defined to encompass the capacitor structure;
• a monocrystalline silicon substrate bonded to the first substrate and over the conductive storage node mass;
• a transistor gate on the monocrystalline silicon substrate and operatively connected with the capacitor structure to define a DRAM cell;
• and
• wherein the cell plate layer comprises:
• a conductive material layer over an insulative material base;
• and
• at least one conductive projection extending upwardly from the conductive material layer.

A semiconductor structure, comprising:

• a cell plate layer;
• a dielectric material over the cell plate layer;
• a conductive storage node mass over the dielectric material;
• the conductive storage node mass, dielectric material and cell plate layer together defining a capacitor structure;
• a first substrate being defined to encompass the capacitor structure;
• a monocrystalline silicon substrate bonded to the first substrate and over the conductive storage node mass;
• a transistor gate on the monocrystalline silicon substrate and operatively connected with the capacitor structure to define a DRAM cell;
• wherein the cell plate layer comprises:
• a first conductive material layer over an insulative material base;
• a second conductive material over the first conductive material and defining a conductive projection extending upwardly from the first conductive material layer, the conductive projection comprising a top surface and sidewall surfaces extending from the first conductive material layer to the top surface;
• wherein the dielectric material extends over the top surface and along the sidewall surfaces of the conductive projection;
• and
• wherein the conductive storage node mass extends over the top surface and along the sidewall surfaces of the conductive projection.