Method for forming a top interconnection level and bonding pads on an integrated circuit chip

A method for forming a top interconnection level and bonding pads of an integrated circuit comprising:

• (a) providing a silicon wafer substrate having integrated circuit devices and a first interconnection level;
• (b) depositing an insulative layer;
• (c) forming trenches and via openings exposing elements of said first interconnection level in said insulative layer;
• (d) depositing a layer of conductive material on said insulative layer;
• (e) polishing said layer of conductive material until a residual thickness of said layer of conductive material remains on the surface of said insulative layer;
• (f) patterning a plurality of bonding pads in said residual thickness of said layer of conductive material, each one of said plurality of bonding pads lying over and contiguous with a segment of said conductive material in said trenches, thereby forming a second interconnection level containing conductive lines in said trenches with a plurality of segments to which superjacent bonding pads are attached;
• (g) depositing a passivation layer;
• and
• (h) patterning said passivation layer to form an access opening over each one of said plurality of bonding pads.